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application note v850e/ma1, v850e/ma2, v850e/ma3, v850e/me2 32-bit single-chip microcontrollers pci host bridge macro document no. u17121ej1v1an00 (1st edition) date published september 2004 n cp(k) printed in japan 2004 v850e/ma1: v850e/ma2: v850e/ma3: v850e/me2: pd703103a pd703108 pd703131a pd703111a pd703105a pd703131ay pd703106a pd703132a pd703106a(a) pd703132ay pd703107a pd703133a pd703107a(a) pd703133ay pd70f3107a pd703134a pd70f3107a(a) pd703134ay pd70f3134a pd70f3134ay
application note u17121ej1v1an 2 [memo]
application note u17121ej1v1an 3 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6
application note u17121ej1v1an 4 the copyright of the pci host bridge macro described in this document is held by the system interface module development department, device soluti ons division, nec engineering, ltd. green hills software and multi are tradem arks of green hills software, inc. these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. the information in this document is current as of march, 2004. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) (1) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. (2) "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). ? ? ? ? ? ? m8e 02. 11-1
application note u17121ej1v1an 5 regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [global support] http://www.necel.com/en/support/support.html nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 nec electronics hong kong ltd. hong kong tel: 2886-9318 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-558-3737 nec electronics shanghai ltd. shanghai, p.r. china tel: 021-5888-5400 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 j04.1 n ec electronics (europe) gmbh duesseldorf, germany tel: 0211-65030 ? sucursal en espa?a madrid, spain tel: 091-504 27 87 v?lizy-villacoublay, france tel: 01-30-67 58 00 ? succursale fran?aise ? filiale italiana milano, italy tel: 02-66 75 41 ? branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 ? tyskland filial taeby, sweden tel: 08-63 80 820 ? united kingdom branch milton keynes, uk tel: 01908-691-133 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify:
application note u17121ej1v1an 6 introduction readers this application note is intended for users who wish to understand t he functions of the v850e/ma1, v850e/ma2, v850e/ma3, v850e/me2, and pci bus to design application systems using these products. purpose the purpose of this applicat ion note is to help the user understand the pci host bridge macro and its composition using t he v850e/ma1, v850e/ma2, v850e/ma3, v850e/me2, and pci host bridge macro as a system example. organization this application note is broadly di vided into the following sections. ? overview of each product ? overview of pci host bridge macro ? specifications of pci host bridge macro ? configuration examples of fpga integration ? application examples how to read this manual it is assumed that the readers of this application note have gener al knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. for details of the hardware functions and electrical specif ications of the v850e/ma1, v850e/ma2, v850e/ma3, and v850e/me2 refer to the hardware user?s manual of each product. for details of the instruction functions of the v850e/ma1, v850e/ma2, v850e/ma3, and v850e/me2 refer to the v850e1 architecture user?s manual . conventions data significance: higher digits on the left and lower digits on the right active low representation: xxx (overscore over pin or signal name) or /xxx (?/? before signal name) memory map address: higher addresse s on the top and lower addresses on the bottom note: footnote for item marked with note in the text caution: information requiring particular attention remark: supplementary information numeric representation: binary ... xxxx or xxxxb decimal ... xxxx hexadecimal ... xxxxh prefix indicating power of 2 ( address space, memory capacity): k (kilo) ... 2 10 = 1,024 m (mega) ... 2 20 = 1,024 2 g (giga) ... 2 30 = 1,024 3
application note u17121ej1v1an 7 related documents the related documents indicated in this pub lication may include preliminary versions. however, preliminary versions are not marked as such. documents related to v850e/ma1, v850e/ma2, v850e/ma3, and v850e/me2 document name document no. v850e1 architecture user?s manual u14559e v850e/ma1 hardware user?s manual u14359e v850e/ma1 hardware application note u15179e v850e/ma2 hardware user?s manual u14980e v850e/ma3 hardware user?s manual u16397e v850e/me2 hardware user?s manual u16031e v850e/me2 hardware application note u16794e v850e/me2 usb function driver application note u17069e v850e/ma1, v850e/ma2, v850e/ma3, v850e/me2 pci ho st bridge macro application note this manual documents related to developm ent tools (user?s manuals) document name document no. ie-v850e-mc, ie-v850e-mc-a in-circuit emulator u14487e ie-703107-mc-em1 in-circuit emulator option board u14481e ie-v850e1-cd-nw pcmcia card ty pe on-chip debug emulator u16647e operation u16053e c language u16054e ca850 ver.2.50 c compiler package assembly language u16042e pm plus ver.5.20 u16934e id850 ver.2.50 integrated debugger operation u16217e id850nw ver.2.51 integrated debugger operation u16454e sm850 ver.2.40 system simulator operation u15182e sm850 ver.2.00 or later system simulator external part user open interfac e specifications u14873e basics u13430e installation u13410e rx850 ver.3.13 or later real-time os technical u13431e basics u13773e installation u13774e rx850 pro ver.3.15 real-time os technical u13772e rd850 ver.3.01 task debugger u13737e rd850 pro ver.3.01 task debugger u13916e az850 ver.3.10 system performance analyzer u14410e pg-fp4 flash memory programmer u15260e
application note u17121ej1v1an 8 contents chapter 1 overview of each product..................................................................................10 1.1 outline .................................................................................................................... .......................10 1.2 features................................................................................................................... ......................11 1.3 ordering information....................................................................................................... .............12 1.4 pin configuration.......................................................................................................... ................14 1.5 internal block diagram ..................................................................................................... ...........25 chapter 2 overview of pci host bridge macro..............................................................29 2.1 outline .................................................................................................................... .......................29 2.2 features................................................................................................................... ......................30 chapter 3 specifications of pci host bridge macro ...................................................31 3.1 internal blocks of pci host bridge macro ................. ................................................................31 3.2 relationship between internal blocks and signals .. ................................................................32 3.3 pin functions .............................................................................................................. ..................33 3.3.1 external bus sl ave interf ace pins ........................................................................................ ...............33 3.3.2 sdram bus interfac e pi ns ................................................................................................. ................33 3.3.3 pci bus in terface pins ................................................................................................... .....................34 3.4 registers .................................................................................................................. .....................35 3.4.1 pci_config_ data r egister................................................................................................. ............35 3.4.2 pci_config_ add regi ster.................................................................................................. .............36 3.4.3 pci_cont rol regi ster..................................................................................................... ................37 3.4.4 pci_io_ base regi ster..................................................................................................... ..................38 3.4.5 pci_mem_ base regi ster .................................................................................................... ..............38 3.4.6 pci_int_ ctl regi ster..................................................................................................... ...................39 3.4.7 pci_err_ add regi ster ..................................................................................................... ................40 3.4.8 system_mem _base regi ster ................................................................................................. ........41 3.4.9 system_mem_r ange re gister ................................................................................................ ......41 3.4.10 sdram_ ctl regi ster ...................................................................................................... ..................42 3.5 address map ................................................................................................................ .................44 3.6 initializing pci host bridge macro ........................... .............................................................. .....45 3.7 bus width of external bus in terface ........................................................................................ ..46 3.8 timing ..................................................................................................................... .......................47 3.8.1 external bus interface timing............................................................................................ ..................47 3.8.2 pci bus in terface timing ................................................................................................. ....................50 chapter 4 configuration examples of fpga integration..........................................57 4.1 conditions for configuration e xamples of fpga integration .................................................57 4.2 points to remember when crea ting top layer of fpga ................. .......................................57 4.3 reference diagram for fpga top connection .........................................................................58 4.4 fpga top pin functions ..................................................................................................... ........59 4.4.1 cpu bus slav e interfac e pins ............................................................................................. ................59 4.4.2 sdram bus interfac e pi ns ................................................................................................. ................59 4.4.3 pci bus in terface pins ................................................................................................... .....................60 4.5 fpga top pin configuration................................................................................................. ......61
application note u17121ej1v1an 9 4.5.1 internal connect ion diagram of exter nal bus in terface .................................................................... ... 61 4.5.2 internal conne ction diagram of pc i bus inte rface ......................................................................... ..... 62 4.5.3 external connection diagram of external bus interface (exa mple of connection with v850e/me2).... 63 4.5.4 external conne ction diagram of pc i bus inte rface ......................................................................... .... 64 4.6 cautions on designing fpga ................................................................................................. ....65 4.6.1 fpga fi tting des ign...................................................................................................... ...................... 65 4.6.2 pci bus interface timing parameters (as constraint of pci clk = 33 mhz) ....................................... 65 4.6.3 sdram inte rface ti ming ................................................................................................... ................. 66 chapter 5 application examples............................................................................................. .67 5.1 block diagram of evaluation board .......................................................................................... .67 5.2 specifications of evaluation board............................ ............................................................. ...68 5.3 example of evaluation board connect ion circuit ....................................................................69 5.4 evaluation board memory space .................................... .......................................................... .70 5.5 sample program examples .................................................................................................... .....72 5.5.1 developm ent t ools ........................................................................................................ ..................... 72 5.5.2 program co nfiguration .................................................................................................... ................... 72 5.5.3 v850e/me2 pci host bridge macro initialization sample program list ............................................... 73 5.5.4 pci configurat ion space access samp le progra m list ....................................................................... .76 5.5.5 ide hdd access sa mple prog ram list....................................................................................... ......... 79
application note u17121ej1v1an 10 chapter 1 overview of each product the v850e/ma1, v850e/ma2, v850e/ma3, and v850e/me2 ar e products in nec electronics? v850 series of single-chip microcontrollers. this chapt er gives a simple outline of each product. 1.1 outline the v850e/ma1, v850e/ma2, v850e/ma3, and v850e/me2 are 32-bit single-chip microcontrollers that integrate the v850e1 cpu, which is a 32-bit risc-type cpu core for asic, newly developed as the cpu core central to system lsi in the current age of system- on-chip. these devices incorporate me mory and various peripheral functions such as memory controllers, a dma controller, timer/count ers, serial interfaces, and an a/d converter for realizing high-capacity data processing and sophisticated real-time control.
chapter 1 overview of each product application note u17121ej1v1an 11 1.2 features commercial name v850e/ma1 v850e/ma2 v850e/ma3 v850e/me2 maximum operating frequency 50 mhz 40 mhz 80 mhz 150 mhz mask rom ? 128 256 ? ? 256 512 ? ? flash memory ? 256 ? ? 512 ? internal memory (kb) ram 4 10 4 16 32 16 32 instruction ram: 128 data ram: 16 cache (kb) ? instruction cache: 8 bus type separate separate separate/multiplexed separate address bus 26 bits 25 bits 26 bits 26 bits data bus 8/16 bits 8/16 bits 8/16 bits 16/32 bits external bus chip select signals 8 4 8 8 memory controller sdram, edo dram, sram, etc. sdram, sram, etc. external note 1 17 (17) 4 (4) 26 (26) 40 (31) interrupts internal 41 27 49 59 32 32 64 20 to 40 ns (50 mhz) 25 to 50 ns (40 mhz) 12.5 to 25 ns (80 mhz) 6.7 to 13.3 ns (150 mhz) dsp function 32 32 + 32 32 60 ns (50 mhz) 75 ns (40 mhz) 37.5 ns (80 mhz) 20 ns (150 mhz) tmc 4 ch 2 ch ? 6 ch tmp ? ? 3 ch ? tmq ? ? 1 ch ? interval timer 4 ch 4 ch 4 ch 4 ch 16-bit timer up/down counter ? ? 1 ch 2 ch watchdog timer ? ? 1 ch ? csi 1 ch ? ? 1 ch uart 1 ch ? ? 1 ch csi/uart 2 ch 2 ch 3 ch 1 ch serial interface uart/i 2 c ? ? 1 ch note 2 ? 10-bit a/d converter 8 ch 4 ch 8 ch 8 ch 8-bit d/a converter ? ? 2 ch ? dma controller 4 ch 4 ch 4 ch 4 ch cmos input 9 5 11 7 ports cmos i/o 106 74 101 77 debug functions ? ? provided (run, break) provided (run, break, trace) other peripheral functions pwm 2 ch ? rom correction function usb function, sscg, pwm 2 ch power supply voltage 3.0 to 3.6 v 2.3 to 2.7 v (internal) 3.0 to 3.6 v (external) 1.5 v (internal) 3.3 v (external) power consumption (mask version typ.) 528 mw 416 mw 575 mw 200 mw package 144-pin lqfp (20 20) 161-pin fbga (13 13) 100-pin lqfp (14 14) 144-pin lqfp (20 20) 161-pin fbga (13 13) 176-pin lqfp (20 20) 240-pin fbga (16 16) operating ambient temperature t a = ? 40 to +85 c t a = ? 40 to +85 c (@133 mhz) t a = ? 40 to +70 c (@150 mhz) notes 1. the figure in parentheses indicates the number of external interrupts that can release stop mode. 2. available only in on-chip i 2 c products (y products).
chapter 1 overview of each product application note u17121ej1v1an 12 1.3 ordering information (1) v850e/ma1 part number package internal rom pd703103agj-uen 144-pin plastic lqfp (fine pitch) (20 20) romless pd703105agj-xxx-uen 144-pin plastic lqfp (fine pitch) (20 20) mask rom (128 kb) pd703106agj-xxx-uen 144-pin plastic lqfp (fine pitch) (20 20) mask rom (128 kb) pd703106agj(a)-xxx-uen 144-pin plastic lqfp (fine pitch) (20 20) mask rom (128 kb) pd703106af1-xxx-en4 161-pin plastic fbga (13 13) mask rom (128 kb) pd703107agj-xxx-uen 144-pin plastic lqfp (fine pitch) (20 20) mask rom (256 kb) pd703107agj(a)-xxx-uen 144-pin plastic lqfp (fine pitch) (20 20) mask rom (256 kb) pd703107af1-xxx-en4 161-pin plastic fbga (13 13) mask rom (256 kb) pd70f3107agj-uen 144-pin plastic lqfp (fine pitch) (20 20) flash memory (512 kb) pd70f3107agj(a)-uen 144-pin plastic lqfp (fine pitch) (20 20) flash memory (512 kb) pd70f3107af1-en4 161-pin plastic fbga (13 13) flash memory (512 kb) (2) v850e/ma2 part number package internal rom pd703108gc-8eu 100-pin plastic lqfp (fine pitch) (14 14) romless
chapter 1 overview of each product application note u17121ej1v1an 13 (3) v850e/ma3 part number package internal rom pd703131agj-xxx-uen 144-pin plastic lqfp (fine pitch) (20 20) mask rom (256 kb) pd703131af1-xxx-en4 161-pin plastic fbga (13 13) mask rom (256 kb) pd703131aygj-xxx-uen 144-pin plastic lqfp (fine pitch) (20 20) mask rom (256 kb) pd703131ayf1-xxx-en4 161-pin plastic fbga (13 13) mask rom (256 kb) pd703132agj-xxx-uen 144-pin plastic lqfp (fine pitch) (20 20) mask rom (256 kb) pd703132af1-xxx-en4 161-pin plastic fbga (13 13) mask rom (256 kb) pd703132aygj-xxx-uen 144-pin plastic lqfp (fine pitch) (20 20) mask rom (256 kb) pd703132ayf1-xxx-en4 161-pin plastic fbga (13 13) mask rom (256 kb) pd703133agj-xxx-uen 144-pin plastic lqfp (fine pitch) (20 20) mask rom (512 kb) pd703133af1-xxx-en4 161-pin plastic fbga (13 13) mask rom (512 kb) pd703133aygj-xxx-uen 144-pin plastic lqfp (fine pitch) (20 20) mask rom (512 kb) pd703133ayf1-xxx-en4 161-pin plastic fbga (13 13) mask rom (512 kb) pd703134agj-xxx-uen 144-pin plastic lqfp (fine pitch) (20 20) mask rom (512 kb) pd703134af1-xxx-en4 161-pin plastic fbga (13 13) mask rom (512 kb) pd703134aygj-xxx-uen 144-pin plastic lqfp (fine pitch) (20 20) mask rom (512 kb) pd703134ayf1-xxx-en4 161-pin plastic fbga (13 13) mask rom (512 kb) pd70f3134agj-uen 144-pin plastic lqfp (fine pitch) (20 20) flash memory (512 kb) pd70f3134af1-en4 161-pin plastic fbga (13 13) flash memory (512 kb) pd70f3134aygj-uen 144-pin plasti c lqfp (fine pitch) (20 20) flash memory (512 kb) pd70f3134ayf1-en4 161-pin plastic fbga (13 13) flash memory (512 kb) (4) v850e/me2 part number package maximum operating frequency pd703111agm-10-ueu 176-pin plastic lqfp (fine pitch) (24 24) 100 mhz pd703111agm-13-ueu 176-pin plastic lqfp (fine pitch) (24 24) 133 mhz pd703111agm-15-ueu 176-pin plastic lqfp (fine pitch) (24 24) 150 mhz pd703111af1-10-ga3 240-pin plastic fbga (16 16) 100 mhz pd703111af1-13-ga3 240-pin plastic fbga (16 16) 133 mhz pd703111af1-15-ga3 240-pin plastic fbga (16 16) 150 mhz
chapter 1 overview of each product application note u17121ej1v1an 14 1.4 pin configuration (1) v850e/ma1 ? 144-pin plastic lqfp (fine pitch) (20 20) pd703103agj-uen pd703106agj(a)-xxx-uen pd70f3107agj-uen pd703105agj-xxx-uen pd703107agj-xxx-uen pd70f3107agj(a)-uen pd703106agj-xxx-uen pd703107agj(a)-xxx-uen top view d14/pdl14 d13/pdl13 d12/pdl12 d11/pdl11 d10/pdl10 d9/pdl9 d8/pdl8 v dd v ss d7/pdl7 d6/pdl6 d5/pdl5 d4/pdl4 d3/pdl3 d2/pdl2 d1/pdl1 d0/pdl0 mode2 (v pp /mode2) dmarq3/intp103/p07 dmarq2/intp102/p06 dmarq1/intp101/p05 dmarq0/intp100/p04 to00/p03 intp001/p02 ti000/intp000/p01 pwm0/p00 v dd v ss dmaak3/pbd3 dmaak2/pbd2 dmaak1/pbd1 dmaak0/pbd0 to01/p13 intp011/p12 ti010/intp010/p11 pwm1/p10 pcd3/ube/sdras pcs0/cs0 pcs1/cs1/ras1 pcs2/cs2/iowr pcs3/cs3/ras3 pcs4/cs4/ras4 pcs5/cs5/iord pcs6/cs6/ras6 pcs7/cs7 v ss v dd pct0/lcas/lwr/ldqm pct1/ucas/uwr/udqm pct4/rd pct5/we pct6/oe pct7/bcyst pcm0/wait pcm1/clkout/busclk pcm2/hldak pcm3/hldrq pcm4/refrq pcm5/selfref p50/intp030/ti030 p51/intp031 p52/to03 v ss v dd p70/ani0 p71/ani1 p72/ani2 p73/ani3 p74/ani4 p75/ani5 p76/ani6 p77/ani7 v dd v ss tc3/intp113/p27 tc2/intp112/p26 tc1/intp111/p25 tc0/intp110/p24 to02/p23 intp021/p22 ti020/intp020/p21 nmi/p20 v dd v ss adtrg/intp123/p37 intp122/p36 intp121/p35 rxd2/intp120/p34 txd2/intp133/p33 sck2/intp132/p32 si2/intp131/p31 so2/intp130/p30 mode1 mode0 reset cksel cv dd x2 x1 cv ss sck1/p45 rxd1/si1/p44 txd1/so1/p43 sck0/p42 rxd0/si0/p41 txd0/so0/p40 av dd /av ref av ss pdl15/d15 pal0/a0 pal1/a1 pal2/a2 pal3/a3 pal4/a4 pal5/a5 pal6/a6 pal7/a7 v ss v dd pal8/a8 pal9/a9 pal10/a10 pal11/a11 pal12/a12 pal13/a13 pal14/a14 pal15/a15 v ss v dd pah0/a16 pah1/a17 pah2/a18 pah3/a19 pah4/a20 pah5/a21 pah6/a22 pah7/a23 pah8/a24 pah9/a25 v ss v dd pcd0/sdcke pcd1/sdclk pcd2/lbe/sdcas 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 remark items in parentheses are pin names in the pd70f3107a.
chapter 1 overview of each product application note u17121ej1v1an 15 ? 161-pin plastic fbga (13 13) pd703106af1-xxx-en4 pd703107af1-xxx-en4 pd70f3107af1-en4 14 13 12 11 10 9 8 7 6 5 4 3 2 1 top view bottom view pnmlk jhgfedcba abcdefghj klmnp index mark index mark (1/2) pin no. name pin no. name pin no. name a1 ? b9 a18/pah2 d3 d14/pdl14 a2 d15/pdl15 b10 a21/pah5 d4 a3/pal3 a3 a2/pal2 b11 a25/pah9 d5 a6/pal6 a4 a5/pal5 b12 sdclk/pcd1 d6 a10/pal10 a5 ? b13 cs1/ras1/pcs1 d7 a14/pal14 a6 a9/pal9 b14 ? d8 a16/pah0 a7 a12/pal12 c1 ? d9 a20/pah4 a8 a15/pal15 c2 d9/pdl9 d10 a23/pah7 a9 a17/pah1 c3 d13/pdl13 d11 sdcke/pcd0 a10 ? c4 a1/pal1 d12 cs0/pcs0 a11 a24/pah8 c5 a7/pal7 d13 cs5/iord/pcs5 a12 v dd c6 v dd d14 ? a13 lbe/sdcas/pcd2 c7 a11/pal11 e1 d5/pdl5 a14 ube/sdras/pcd3 c8 v dd e2 d7/pdl7 b1 ? c9 a19/pah3 e3 d8/pdl8 b2 d12/pdl12 c10 a22/pah6 e4 d11/pdl11 b3 a0/pal0 c11 v ss e5 ? b4 a4/pal4 c12 cs3/ras3/pcs3 e11 cs6/ras6/pcs6 b5 v ss c13 cs2/iowr/pcs2 e12 cs4/ras4/pcs4 b6 a8/pal8 c14 ? e13 cs7/pcs7 b7 a13/pal13 d1 v ss e14 v ss b8 v ss d2 d10/pdl10 f1 d2/pdl2
chapter 1 overview of each product application note u17121ej1v1an 16 (2/2) pin no. name pin no. name pin no. name f2 d3/pdl3 k2 v ss m12 ani6/p76 f3 d4/pdl4 k3 dmaak1/pbd1 m13 ani5/p75 f4 v dd k4 dmaak3/pbd3 m14 ? f11 rd/pct4 k11 ani1/p71 n1 ? f12 v dd k12 ani0/p70 n2 pwm1/p10 f13 lcas/lwr/ldqm/pct0 k13 v ss n3 tc3/intp113/p27 f14 ucas/uwr/udqm/pct1 k14 v dd n4 tc0/intp110/p24 g1 mode2 (mode2/v pp ) l1 ? n5 nmi/p20 g2 dmarq3/intp103/p07 l2 dmaak2/pbd2 n6 adtrg/intp123/p37 g3 d0/pdl0 l3 ti010/intp010/p11 n7 txd2/intp133/p33 g4 d6/pdl6 l4 dmaak0/pbd0 n8 so2/intp130/p30 g11 wait/pcm0 l5 to02/p23 n9 x2 g12 we/pct5 l6 v dd n10 cv ss g13 bcyst/pct7 l7 intp122/p36 n11 sck0/p42 g14 oe/pct6 l8 si2/intp131/p31 n12 av dd /av ref h1 dmarq2/intp102/p06 l9 reset n13 av ss h2 dmarq1/intp101/p05 l10 txd1/so1/p43 n14 ? h3 dmarq0/intp100/p04 l11 ani7/p77 p1 v dd h4 d1/pdl1 l12 ani4/p74 p2 v ss h11 refrq/pcm4 l13 ani3/p73 p3 tc1/intp111/p25 h12 hldrq/pcm3 l14 ani2/p72 p4 intp021/p22 h13 hldak/pcm2 m1 ? p5 ? h14 clkout/busclk/pcm1 m2 intp011/p12 p6 intp121/p35 j1 to00/p03 m3 to01/p13 p7 sck2/intp132/p32 j2 ti000/intp000/p01 m4 tc2/intp112/p26 p8 mode1 j3 v dd m5 ti020/intp020/p21 p9 cv dd j4 intp001/p02 m6 v ss p10 x1 j11 to03/p52 m7 rxd2/intp120/p34 p11 ? j12 ti030/intp030/p50 m8 mode0 p12 rxd1/si1/p44 j13 selfref/pcm5 m9 cksel p13 rxd0/si0/p41 j14 intp031/p51 m10 sck1/p45 p14 ? k1 pwm0/p00 m11 txd0/so0/p40 remarks 1. leave the a1, a5, a10, b1, b14, c1, c14, d14, e5, l1, m1, m14, n1, n14, p5, p11, and p14 pins open. 2. items in parentheses are pin names in the pd70f3107a.
chapter 1 overview of each product application note u17121ej1v1an 17 (2) v850e/ma2 ? 100-pin plastic lqfp (fine pitch) (14 14) pd703108gc-8eu top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 a1/pal1 a0/pal0 d15/pdl15 d14/pdl14 d13/pdl13 d12/pdl12 d11/pdl11 d10/pdl10 d9/pdl9 d8/pdl8 v dd v ss d7/pdl7 d6/pdl6 d5/pdl5 d4/pdl4 d3/pdl3 d2/pdl2 d1/pdl1 d0/pdl0 mode2 dmarq1/intp101/p05 dmarq0/intp100/p04 to00/p03 intp001/p02 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 pah7/a23 pah8/a24 pcd0/sdcke pcd1/sdclk pcd2/lbe/sdcas pcd3/ube/sdras pcs0/cs0 pcs3/cs3 pcs4/cs4 pcs7/cs7 pct0/lwr/ldqm pct1/uwr/udqm pct4/rd pct5/we pcm0/wait pcm1/clkout pcm2/hldak pcm3/hldrq pcm4/refrq v ss v dd p70/ani0 p71/ani1 p72/ani2 p73/ani3 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 pal2/a2 pal3/a3 pal4/a4 pal5/a5 pal6/a6 pal7/a7 v ss v dd pal8/a8 pal9/a9 pal10/a10 pal11/a11 pal12/a12 pal13/a13 pal14/a14 pal15/a15 v ss v dd pah0/a16 pah1/a17 pah2/a18 pah3/a19 pah4/a20 pah5/a21 pah6/a22 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 ti000/intp000/p01 dmaak1/pbd1 dmaak0/pbd0 intp011/p12 ti010/intp010/p11 tc0/intp110/p24 nmi/p20 v dd v ss mode1 mode0 reset cksel cv dd x2 x1 cv ss sck1/p45 rxd1/si1/p44 txd1/so1/p43 sck0/p42 rxd0/si0/p41 txd0/so0/p40 av dd /a ref av ss
chapter 1 overview of each product application note u17121ej1v1an 18 (3) v850e/ma3 ? 144-pin plastic lqfp (fine pitch) (20 20) pd703131agj-xxx-uen pd703133agj-xxx-uen pd70f3134agj-uen pd703131aygj-xxx-uen pd703133aygj-xxx-uen pd70f3134aygj-uen pd703132agj-xxx-uen pd703134agj-xxx-uen pd703132aygj-xxx-uen pd703134aygj-xxx-uen top view ad14/pdl14 ad13/pdl13 ad12/pdl12 ad11/pdl11 ad10/pdl10 ad9/pdl9 ad8/pdl8 ev dd ev ss ad7/pdl7 ad6/pdl6 ad5/pdl5 ad4/pdl4 ad3/pdl3 ad2/pdl2 ad1/pdl1 ad0/pdl0 intp001/top01/intpp01/p01 intp000/top00/evtp0/tip0/intpp00/p00 intp115/toqb3/evtq/p15 intp114/toqb2/tiq/p14 intp013/toqt3/intpq3/toq3/p13 v dd v ss intp012/toqt2/intpq2/toq2/p12 intp011/toqt1/intpq1/toq1/p11 intp010/toqb1/intpq0/toq0/p10 tdo/tc3/p27 tdi/intp126/tc2/p26 intp125/tc1/tiud10/to10/p25 intp124/tc0/p24 trst intp004/dmarq0/tclr10/intp11/p04 intp005/dmarq1/tcud10/intp10/p05 tms/intp106/dmarq2/p06 tck/intp107/dmarq3/p07 pcd3/sdras pcs0/cs0 pcs1/cs1 pcs2/cs2/iowr pcs3/cs3 pcs4/cs4 pcs5/cs5/iord pcs6/cs6 pcs7/cs7 ev ss ev dd pct0/lbe/lwr/ldqm pct1/ube/uwr/udqm pct4/rd pct5/wr/we pct6/astb pct7/bcyst pcm0/wait pcm1/busclk pcm2/hldak pcm3/hldrq pcm4/refrq p50/intp050/intpp20/top20/evtp2/tip2 p51/intp051/intpp21/top21 p20/nmi p37/intp137/adtrg v ss v dd p70/ani0 p71/ani1 p72/ani2 p73/ani3 p74/ani4 p75/ani5 p76/ani6 p77/ani7 ev dd ev ss dmaak3/pbd3 dmaak2/pbd2 dmaak1/pbd1 dmaak0/pbd0 intp022/top11/intpp11/p22 intp021/top10/evtp1/tip1/intpp10/p21 intp134/rxd3/scl note /p34 intp133/txd3/sda note /p33 intp132/asck2/sck2/p32 intp131/rxd2/si2/p31 intp130/txd2/so2/p30 asck1/sck1/p45 rxd1/si1/p44 txd1/so1/p43 asck0/sck0/p42 rxd0/si0/p41 txd0/so0/p40 cv dd x2 x1 cv ss cksel psel v dd v ss mode0 mode1 reset av dd1 ano1/p81 ano0/p80 av ss1 av ss0 av dd0 pdl15/ad15 pal0/a0 pal1/a1 pal2/a2 pal3/a3 pal4/a4 pal5/a5 pal6/a6 pal7/a7 ev ss ev dd pal8/a8 pal9/a9 pal10/a10 pal11/a11 pal12/a12 pal13/a13 pal14/a14 pal15/a15 v ss v dd pah0/a16 pah1/a17 pah2/a18 pah3/a19 pah4/a20 pah5/a21 pah6/a22 pah7/a23 pah8/a24 pah9/a25 ev ss ev dd pcd0/sdcke pcd1/sdclk pcd2/sdcas 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 note scl and sda are available only in the pd703131y, 703132y, 703133y, 703134y, 703137y, and 70f3134y.
chapter 1 overview of each product application note u17121ej1v1an 19 ? 161-pin plastic fbga (13 13) pd703131af1-en4 pd703133af1-xxx-en4 pd70f3134af1-en4 pd703131ayf1-xxx-en4 pd703133ayf1-xxx-en4 pd70f3134ayf1-en4 pd703132af1-xxx-en4 pd703134af1-xxx-en4 pd703132ayf1-xxx-en4 pd703134ayf1-xxx-en4 14 13 12 11 10 9 8 7 6 5 4 3 2 1 top view bottom view pnmlk jhgfedcba abcdefghj klmnp index mark index mark (1/2) pin no. name pin no. name pin no. name a1 ev ss b8 v ss d1 ev ss a2 ad15/pdl15 b9 a18/pah2 d2 ad10/pdl10 a3 a2/pal2 b10 a21/pah5 d3 ad14/pdl14 a4 a5/pal5 b11 a25/pah9 d4 a3/pal3 a5 ev ss b12 sdclk/pcd1 d5 a6/pal6 a6 a9/pal9 b13 cs1/pcs1 d6 a10/pal10 a7 a12/pal12 b14 ev ss d7 a14/pal14 a8 a15/pal15 c1 ev ss d8 a16/pah0 a9 a17/pah1 c2 ad9/pdl9 d9 a20/pah4 a10 ? c3 ad13/pdl13 d10 a23/pah7 a11 a24/pah8 c4 a1/pal1 d11 sdcke/pcd0 a12 ev dd c5 a7/pal7 d12 cs0/pcs0 a13 sdcas/pcd2 c6 ev dd d13 cs5/iord/pcs5 a14 sdras/pcd3 c7 a11/pal11 d14 ev ss b1 ev ss c8 v dd e1 ad5/pdl5 b2 ad12/pdl12 c9 a19/pah3 e2 ad7/pdl7 b3 a0/pal0 c10 a22/pah6 e3 ad8/pdl8 b4 a4/pal4 c11 ev ss e4 ad11/pdl11 b5 ev ss c12 cs3/pcs3 e5 ? b6 a8/pal8 c13 cs2/iowr/pcs2 e11 cs6/pcs6 b7 a13/pal13 c14 ev ss e12 cs4/pcs4
chapter 1 overview of each product application note u17121ej1v1an 20 (2/2) pin no. name pin no. name pin no. name e13 cs7/pcs7 j14 nmi/p20 m11 av ss0 e14 ev ss k1 toqt1/intp011/intpq1/toq1/p11 m12 ani6/p76 f1 ad2/pdl2 k2 tc3/tdo/p27 m13 ani5/p75 f2 ad3/pdl3 k3 tc0/intp124/p24 m14 ? f3 ad4/pdl4 k4 tc2/tdi/intp126/p26 n1 ev ss f4 ev dd k11 ani1/p71 n2 dmarq3/tck/intp107/p07 f11 rd/pct4 k12 ani0/p70 n3 dmaak3/pbd3 f12 ev dd k13 v ss n4 dmaak0/pbd0 f13 lbe/lwr/ldqm/pct0 k14 v dd n5 txd3/sda note /intp133/p33 f14 ube/uwr/udqm/pct1 l1 ev ss n6 txd2/so2/intp130/p30 g1 top01/intp001/intpp01/p01 l2 tc1/tiud10/to10/intp125/p25 n7 asck0/sck0/p42 g2 top00/intp000/evtp0/tip0/ intpp00/p00 l3 dmarq2/tms/intp106/p06 n8 v ss g3 ad0/pdl0 l4 trst n9 x2 g4 ad6/pdl6 l5 top11/intpp11/intp022/p22 n10 cv ss g11 wait/pcm0 l6 asck2/sck2/intp132/p32 n11 ano1/p81 g12 wr/we/pct5 l7 asck1/sck1/p45 n12 av ss1 g13 bcyst/pct7 l8 txd0/so0/p40 n13 av dd1 g14 astb/pct6 l9 mode0 n14 ? h1 toqb3/intp115/evtq/p15 l10 av dd0 p1 ev dd h2 toqb2/intp114/tiq/p14 l11 ani7/p77 p2 ev ss h3 toqt3/intp013/intpq3/toq3/p13 l12 ani4/p74 p3 dmaak1/pbd1 h4 ad1/pdl1 l13 ani3/p73 p4 top10/intpp10/evtp1/tip1/ intp021/p21 h11 refrq/pcm4 l14 ani2/p72 p5 ev ss h12 hldrq/pcm3 m1 ev ss p6 rxd1/si1/p44 h13 hldak/pcm2 m2 dmarq1/tcud10/intp10/ intp005/p05 p7 rxd0/si0/p41 h14 busclk/pcm1 m3 dmarq0/intp11/tclr10/ intp004/p04 p8 psel j1 v dd m4 dmaak2/pbd2 p9 cv dd j2 toqt2/intp012/intpq2/toq2/p12 m5 rxd3/scl note /intp134/p34 p10 x1 j3 toqb1/intp010/intpq0/toq0/p10 m6 rxd2/si2/intp131/p31 p11 ? j4 v ss m7 txd1/so1/p43 p12 reset j11 adtrg/intp137/p37 m8 v dd p13 ano0/p80 j12 top21/intpp21/intp051/p51 m9 cksel p14 ? j13 top20/intpp20/evtp2/tip2/ intp050/p50 m10 mode1 note scl and sda are available only in the pd703131ay, 703132ay, 703133ay, 703134ay, and 70f3134ay. remark leave the a10, e5, m14, n 14, p11, and p14 pins open.
chapter 1 overview of each product application note u17121ej1v1an 21 (4) v850e/me2 ? 176-pin plastic lqfp (fine pitch) (24 24) pd703111agm-10-ueu pd703111agm-13-ueu pd703111agm-15-ueu top view 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 trcdata3 pdh15/d31/intpd15/pwm1 pdh14/d30/intpd14/pwm0 ev ss ev dd pdh13/d29/intpd13/tiud11 pdh12/d28/intpd12/to11 pdh11/d27/intpd11/intp111/tclr11 pdh10/d26/intpd10/intp110/tcud11 pdh9/d25/intpd9/tiud10 pdh8/d24/intpd8/to10 pdh7/d23/intpd7/intp101/tclr10 pdh6/d22/intpd6/intp100/tcud10 pdh5/d21/intpd5/toc5 pdh4/d20/intpd4 pdh3/d19/intpd3 ev ss ev dd pdh2/d18/intpd2/toc4 pdh1/d17/intpd1 pdh0/d16/intpd0 d15 d14 d13 d12 d11 d10 d9 d8 iv ss iv dd ev ss ev dd d7 d6 d5 d4 d3 d2 d1 d0 sdcke/pcd0 ev ss ev dd 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 p72/dmarq2/intpc20/tic2 p73/dmaak2/intpc21 p74/tc2/toc2 p75/dmarq3/intpc30/tic3 p76/dmaak3/intpc31 p77/tc3/toc3 ssel0 ssel1 pllv ss pllv dd oscv ss x2 x1 oscv dd uv dd udm udp p10/uclk/intp10 iv ss iv dd pllsel p11/sck0/intp11 p12/rxd0/si0 p13/txd0/so0 p20/nmi ev ss ev dd p21/rxd1/intp21 p22/txd1/intp22 p23/sck1/intp23 p24/si1/intp24 p25/so1/intp25 dck dms drst ddi ddo trcclk trcend trcdata0 trcdata1 iv ss iv dd trcdata2 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 a25/pah9 a24/pah8 a23/pah7 a22/pah6 a21/pah5 a20/pah4 a19/pah3 a18/pah2 ev dd ev ss iv dd iv ss a17/pah1 a16/pah0 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 ev dd ev ss a4 a3 a2 intpl1/a1/pal1 intpl0/a0/pal0 bcyst/pct7 we/wr/pct5 rd/pct4 uudqm/uube/uuwr/pct3 pct2/ulwr/ulbe/uldqm pct1/luwr/lube/ludqm pct0/llwr/llbe/lldqm iv dd iv ss sdras/pcd3 sdcas/pcd2 busclk/pcd1 jit1 jit0 av dd av refp ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 av refm av ss mode1 mode0 intp67/toc1/p67 intp66/intpc11/p66 intp65/tic1/intpc10/p65 toc0/tc1/p55 intpc01/dmaak1/p54 intpc00/tic0/dmarq1/p53 intp52/tc0/p52 intp51/dmaak0/p51 intp50/dmarq0/p50 iv dd iv ss reset adtrg/selfref/pcm5 refrq/pcm4 hldrq/pcm3 hldak/pcm2 pcm1 wait/pcm0 cs7/pcs7 cs6/pcs6 iord/cs5/pcs5 ev dd ev ss cs4/pcs4 cs3/pcs3 iowr/cs2/pcs2 cs1/pcs1 cs0/pcs0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
chapter 1 overview of each product application note u17121ej1v1an 22 ? 240-pin plastic fbga (16 16) pd703111af1-10-ga3 pd703111af1-13-ga3 pd703111af1-15-ga3 bottom view top view 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 index mark efghjklmnprtuv abcd pnmlk jhgfedcba vutr
chapter 1 overview of each product application note u17121ej1v1an 23 (1/2) pin no. name pin no. name pin no. name a1 ? c12 iv dd g3 ev ss a2 iv ss c13 pah2/a18 g4 d7 a3 pct0/llwr/llbe/lldqm c14 pah4/a20 g15 pcm1 a4 ? c15 pah6/a22 g16 pcm3/hldrq a5 pct4/rd c16 ? g17 pcm4/refrq a6 ? c17 pcs0/cs0 g18 pcm5/adtrg/selfref a7 ? c18 ? h1 ? a8 ev dd d1 d0 h2 d8 a9 a9 d2 ev ss h3 d9 a10 ? d3 pcd0/sdcke h4 d10 a11 a14 d4 ev dd h5 iv ss a12 iv ss d5 pct1/luwr/lube/ludqm h14 ? a13 ev dd d6 ? h15 reset a14 ? d7 pal0/intpl0/a0 h16 iv ss a15 pah5/a21 d8 a4 h17 ? a16 pah7/a23 d9 a6 h18 iv dd a17 pah9/a25 d10 ? j1 ? a18 ? d11 a13 j2 d11 b1 ? d12 ev ss j3 d12 b2 pcd1/busclk d13 pah3/a19 j4 ? b3 pcd2/sdcas d14 ? j5 d13 b4 ? d15 ? j14 ? b5 pct3/uuwr/uube/uudqm d16 pcs2/cs2/iowr j15 p50/intp50/dmarq0 b6 pct7/bcyst d17 pcs3/cs3 j16 p51/intp51/dmaak0 b7 a2 d18 ev dd j17 p52/intp52/tc0 b8 ? e1 d3 j18 p53/intpc00/tic0/dmarq1 b9 a8 e2 d2 k1 d14 b10 a12 e3 d1 k2 d15 b11 pah0/a16 e4 ? k3 pdh0/d16/intpd0 b12 ? e8 a3 k4 pdh1/d17/intpd1 b13 ? e9 a5 k5 pdh2/d18/intpd2/toc4 b14 ? e10 a10 k14 p55/toc0/tc1 b15 ? e11 pah1/a17 k15 p54/intpc01/dmaak1 b16 pah8/a24 e15 pcs4/cs4 k16 p65/intp65/intpc10/tic1 b17 ? e16 ev ss k17 p66/intp66/intpc11 b18 pcs1/cs1 e17 pcs5/cs5/iord k18 ? c1 ? e18 pcs6/cs6 l1 ev dd c2 ? f1 d6 l2 ? c3 pcd3/sdras f2 d5 l3 ev ss c4 iv dd f3 d4 l4 pdh3/d19/intpd3 c5 pct2/ulwr/ulbe/uldqm f4 ? l5 pdh4/d20/intpd4 c6 pct5/we/wr f15 ? l14 mode1 c7 pal1/intpl1/a1 f16 pcs7/cs7 l15 ? c8 ev ss f17 pcm0/wait l16 mode0 c9 a7 f18 pcm2/hldak l17 ? c10 a11 g1 iv dd l18 p67/intp67/toc1 c11 a15 g2 ev dd m1 ?
chapter 1 overview of each product application note u17121ej1v1an 24 (2/2) pin no. name pin no. name pin no. name m2 pdh5/d21/intpd5/toc5 r7 dck u4 ? m3 pdh6/d22/intpd6/intp100/ tcud10 r8 ev dd u5 trcclk m4 ? r9 p11/intp11/sck0 u6 drst m15 ani6 r10 iv ss u7 p25/intp25/so1 m16 av refm r11 udm u8 p22/intp22/txd1 m17 ani7 r12 x2 u9 ev ss m18 av ss r13 pllv dd u10 iv dd n1 pdh7/d23/intpd7/intp101/ tclr10 r14 ssel0 u11 ? n2 pdh8/d24/intpd8/to10 r15 ? u12 oscv dd n3 pdh9/d25/intpd9/tiud10 r16 av refp u13 ? n4 pdh10/d26/intpd10/ intp110/tcud11 r17 av dd u14 ? n15 ani2 r18 ? u15 p76/intpc31/dmaak3 n16 ani3 t1 ev dd u16 p73/intpc21/dmaak2 n17 ani4 t2 trcdata3 u17 p72/intpc20/tic2/dmarq2 n18 ani5 t3 ? u18 ? p1 ? t4 trcdata1 v1 ? p2 pdh11/d27/intpd11/ intp111/tclr11 t5 trcend v2 trcdata2 p3 pdh13/d29/intpd13/tiud11 t6 ddi v3 iv ss p4 ? t7 ? v4 trcdata0 p8 p23/intp23/sck1 t8 p21/intp21/rxd1 v5 ? p9 p12/si0/rxd0 t9 p20/nmi v6 dms p10 ? t10 ? v7 p24/intp24/si1 p11 uv dd t11 udp v8 ? p15 ? t12 x1 v9 p13/so0/txd0 p16 ani0 t13 oscv ss v10 pllsel p17 ani1 t14 ssel1 v11 p10/intp10/uclk p18 ? t15 p75/intpc30/tic3/dmarq3 v12 ? r1 pdh12/d28/intpd12/to11 t16 ? v13 ? r2 ev ss t17 jit1 v14 ? r3 pdh14/d30/intpd14/pwm0 t18 jit0 v15 pllv ss r4 iv dd u1 pdh15/d31/intpd15/pwm1 v16 p77/toc3/tc3 r5 ? u2 ? v17 p74/toc2/tc2 r6 ddo u3 ? v18 ? remark leave the a1, a4, a6, a7, a10, a14, a18, b1, b4, b8, b12 to b15, b17, c1, c2, c16, c18, d6, d10, d14, d15, e4, f4, f15, h1, h14, h17, j1, j4, j14, k18, l2, l15, l17, m1, m4, p1, p4, p10, p15, p18, r5, r15, r18, t3, t7, t10, t16, u2 to u4 , u11, u13, u14, u18, v1, v5, v8, v12 to v14, and v18 pins open.
chapter 1 overview of each product application note u17121ej1v1an 25 1.5 internal block diagram (1) v850e/ma1 nmi intp000, intp001, intp010, intp011, intp020, intp021, intp030, intp031 intp100 to intp103, intp110 to intp113, intp120 to intp123, intp130 to intp133 to00 to to03 ti000, ti010, ti020, ti030 intc rpu sio rom note 1 ram note 2 cpu 32-bit barrel shifter pc system registers general- purpose registers (32 bits 32) alu multiplier (32 32 64) ports pdl0 to pdl15 pal0 to pal15 pah0 to pah9 pcs0 to pcs7 pct0, pct1, pct4 to pct7 pcm0 to pcm5 pcd0 to pcd3 pbd0 to pbd3 p70 to p77 p50 to p52 p40 to p45 p30 to p37 p21 to p27 p20 p10 to p13 p00 to p07 cg system controller bcu clkout cksel x1 x2 cv dd cv ss mode0, mode1 mode2/v pp note 3 reset v dd v ss uart0/csi0 uart1/csi1 uart2 csi2 adc so0/txd0 si0/rxd0 sck0 so1/txd1 si1/rxd1 sck1 txd2 rxd2 pwm0 so2 si2 sck2 ani0 to ani7 av ref /av dd av ss adtrg instruction queue memc hldrq hldak cs0, cs7 cs1/ras1, cs3/ras3 cs4/ras4, cs6/ras6 cs2/iord cs5/iowr selfref refrq bcyst lbe/sdcas ube/sdras sdclk sdcke we rd oe uwr/ucas/udqm lwr/lcas/ldqm wait a0 to a25 d0 to d15 busclk dramc dmac romc pwm0 pwm1 pwm1 dmarq0 to dmarq3 dmaak0 to dmaak3 tc0 to tc3 notes 1. pd703103a: romless pd703105a, 703106a: 128 kb (mask rom) pd703107a: 256 kb (mask rom) pd70f3107a: 256 kb (flash memory) 2. pd703103a, 703105a: 4 kb pd703106a, 703107a, 70f3107a: 10 kb 3. available only in the pd70f3107a.
chapter 1 overview of each product application note u17121ej1v1an 26 (2) v850e/ma2 nmi intp000, intp001, intp010, intp011 intp100, intp101, intp110 to00 ti000, ti010 intc rpu sio ram 4 kb cpu 32-bit barrel shifter pc system registers general- purpose registers (32 bits 32) alu multiplier (32 32 64) ports pdl0 to pdl15 pal0 to pal15 pah0 to pah8 pcs0, pcs3, pcs4, pcs7 pct0, pct1, pct4, pct5 pcm0 to pcm4 pcd0 to pcd3 pbd0, pbd1 p70 to p73 p40 to p45 p24 p20 p11, p12 p01 to p05 cg system controller bcu clkout cksel x1 x2 cv dd cv ss mode0 to mode2 reset v dd v ss uart0/csi0 uart1/csi1 adc txd0/so0 rxd0/si0 sck0 txd1/so1 rxd1/si1 sck1 ani0 to ani3 av ref /av dd av ss instruction queue memc hldrq hldak cs0, cs3, cs4, cs7 refrq lbe/sdcas ube/sdras sdclk sdcke we rd uwr/udqm lwr/ldqm wait a0 to a24 d0 to d15 sdramc dmac romc prescaler dmarq0, dmarq1 dmaak0, dmaak1 tc0
chapter 1 overview of each product application note u17121ej1v1an 27 (3) v850e/ma3 nmi toq0 to toq3, toqt1 to toqt3, toqb1 to toqb3 ani0 to ani7 ano0, ano1 tclr10, tiud10, tcud10 intp10, intp11 to10 intp000, intp001, intp004, intp005 intp010 to intp013, intp114, intp115 intp021, intp022, intp124 to intp126 intp130 to intp134, intp137, intp050, intp051, intp106, intp107 intc tmenc 1 ch tmd 4 ch tmq0 1 ch tmp 3 ch uarta0/csib0 uarta1/csib1 adc 8 ch dac 2 ch rom ram note 2 cpu 32-bit barrel shifter pc system registers general- purpose registers (32 bits 32) alu multiplier (32 32 64) ports cg dcu system controller bcu psel cksel x1 x2 cv dd cv ss reset mode0, mode1 v dd v ss ev dd ev ss tck tms trst tdo tdi tiq, evtq, intpq0 to intpq3 evtp0 to evtp2, tip0 to tip2, intpp00, intpp01 intpp10, intpp11, intpp20, intpp21 top00, top01, top10, top11, top20, top21 txd2/so2 rxd2/si2 asck2/sck2 uarta2/csib2 adtrg txd0/so0 rxd0/si0 asck0/sck0 txd1/so1 rxd1/si1 asck1/sck1 av dd0 av ss 0 av dd1 av ss 1 instruction queue memc wait hldrq hldak busclk a0 to a25 ad0 to ad15 cs0 to cs7 bcyst rd uwr, lwr/ube, lbe wr astb iord iowr sdclk sdcke sdras sdcas we ldqm, udqm refrq sram rom dmac sdram wdt uarta3/i 2 c note 3 txd3/sda note 3 rxd3/scl note 3 dmarq0 to dmarq3 dmaak0 to dmaak3 tc0 to tc3 p00, p01, p04 to p07 p10 to p15 p20 p21, p22, p24 to p27 p30 to p34, p37 p40 to p45 p50, p51 p70 to p77 p80, p81 pal0 to pal15 pah0 to pah9 pdl0 to pdl15 pcs0 to pcs7 pct0 to pct7 pcm0 to pcm4 pcd0 to pcd3 pbd0 to pbd3 rom correction note 1 pll notes 1. pd703131a, 703131ay, 703132a, 703132ay: 256 kb (mask rom) pd703133a, 703133ay, 703134a, 703134ay: 512 kb (mask rom) pd70f3134a, 70f3134ay: 512 kb (flash memory) 2. pd703131a, 703131ay, 703133a, 703133ay: 16 kb pd703132a, 703132ay, 703134a, 703134ay, 70f3134a, 70f3134ay: 32 kb 3. available only in the pd703131ay, 703132ay, 703133ay, 70313 4ay, 703137ay, and 70f3134ay.
chapter 1 overview of each product application note u17121ej1v1an 28 (4) v850e/me2 cpu 32-bit barrel shifter pc system registers general- purpose registers (32 bits 32) alu multiplier (32 32 64) ports p10 to p13 p20 p21 to p25 p50 to p55 p65 to p67 p72 to p77 pal0, pal1 pah0 to pah9 pcd0 to pcd3 pcm0 to pcm5 pcs0 to pcs7 pct0 to pct5, pct7 pdh0 to pdh15 adc usbf pwm system controller bcu instruction queue memc sram rom sdram dma si0/rxd0 so0/txd0 sck0 toc4, toc5 toc0 to toc3 tic0 to tic3 to10, to11 nmi drst, dck, dms, ddi, wait hldrq hldak a0 to a25 d0 to d31 dmarq0 to dmarq3 dmaak0 to dmaak3 tc0 to tc3 cs0, cs1, cs3, cs4, cs6, cs7 cs2/iowr cs5/iord bcyst rd ani0 to ani7 adtrg av refp , av refm av dd av ss reset mode0, mode1 iv dd iv ss ev dd ev ss pwm0, pwm1 udp udm uclk uv dd xxwr/xxbe wr busclk sdcke sdras sdcas we xxdqm refrq selfref ddo, trcclk, trcdata0 to trcdata3 , trcend intp100, intp110 intp101, intp111 intp10, intp11 intp21 to intp25 intp50 to intp52 intp65 to intp67 intpd0 to intpd15 intpl0, intpl1 tclr10, tclr11 tiud10, tiud11 tcud10, tcud11 intpc00, intpc01, intpc10, intpc11, intpc20, intpc21, intpc30, intpc31 si1 so1 sck1 rxd1 txd1 ssel0, ssel1 jit0, jit1 pllsel x1 x2 oscv dd oscv ss pllv dd pllv ss tmc tmc tmenc1 intc dcu tmd csi30/uartb0 csi31 uartb1 cg 8 kb instruction cache 128 kb instruction ram 16 kb data ram bbr remark xx: ll, lu, ul, uu
application note u17121ej1v1an 29 chapter 2 overview of pci host bridge macro the pci host bridge macro enables connection of v 850e/ma1, v850e/ma2, v850e/ma3, v850e/me2 external bus interfaces to the pci bus interface. this c hapter gives an outline of the pci host bridge macro. 2.1 outline the pci host bridge macro is a bridge control ma cro that connects v850e/ma1, v850e/ma2, v850e/ma3, v850e/me2 external bus interfaces (memory c ontroller (memc)) to the pci bus interface. the main memory (sdram) can be directly contro lled when sdram is accessed from a pci device.
chapter 2 overview of pci host bridge macro application note u17121ej1v1an 30 2.2 features the features of the pci host bridge macro are as follows. ? pci bus master cycle control pci configuration register read/write single cycle pci i/o register read/write single cycle pci memory read/write single cycle ? pci bus slave cycle control pci memory read/write cycle (burst transfer up to 8 doublewords (32 bits 8 bursts)) ? pci bus arbiter control up to 8 masters can be controlled (one of them is occupied by the pci host bridge macro) bus parking master: limited to pci host bridge ma cro/selectable from the last accessed master ? pci bus error processing an error interrupt is generated for master abo rt/target abort/perr# rec eption/serr# reception the address immediately before an error occurs is retained ? pci bus address conversion control pci i/o address and pci memory address registers are supported to convert the physical addresses from the cpu to addresses for the pci bus ? cpu interface control external bus interface (memc) data bus width: 32 bits/16 bits cycle control by hardware wait control ? sdram control sdram is controlled in response to main memory (sdram) access from the pci device data bus width: 16 bits/32 bits are supported ? pci clock 33 mhz supported sdram control and pci control clocks are designed to be asynchronous
application note u17121ej1v1an 31 chapter 3 specifications of pci host bridge macro this chapter describes the block diagram, signals, register specifications, and operation specifications of the pci host bridge macro. 3.1 internal blocks of pci host bridge macro the pci host bridge macro consists of the four blocks shown in figure 3-1 general blo ck diagram of pci host bridge macro . the functions of each block are described below. (1) lm_bridge: external bus interface master controller this controller is connected to the external bus interf ace, responds to accesses from the cpu, and issues an access request to the ph_flip_bridge block of the pci bus controller. a bus width of 16 bits or 32 bits can be accessed from the cpu. (2) ls_bridge: external bus interface slave controller this controller responds to accesses from the ph_flip_ bridge block of the pci bus controller in response to a memory data transfer request from the pci device and issues an access request to sdramc. (3) sdramc: external bus interface sdram controller this controller is connected to the sdram bus. a memory request from the pci device via the ls_bridge block is transferred by activating the sdram bus. when the bus width of sdram is 16 bits , memory cycles of up to 8 bursts ar e started. when the bus width is 32 bits, memory cycles of up to 4 bursts are started. (4) ph_flip_bridge: external bus interface host controller this controller is connected to the pci bus and operates as the pci host device. a pci configuration register read/write cycle, pci io register read/write cycle, and pci memory read/write cycle are started in response to a r equest from the lm_bridge block. moreover, a request is issued to the ls_bridge block in response to a memory data transfer request from the pci device connected to the pci bus. figure 3-1. general block diag ram of pci host bridge macro pci bus interface pci host bridge macro lm_bridge ph_flip_bridge ls_bridge sdramc external bus interface sdram bus interface
chapter 3 specifications of pci host bridge macro application note u17121ej1v1an 32 3.2 relationship between internal blocks and signals the i/o signals for each block of the pci host bridge macro are as follows. figure 3-2. blocks and pin signa ls of pci host bridge macro lm_bridge ls_bridge sdramc ph_flip_bridge i_pclk o_pcirst_b i_ad0 to i_ad31 o_ad0 to o_ad31 en_ad i_cbe0 to i_cbe3 o_cbe0 to o_cbe3 en_cbe i_frame_b o_frame_b en_frame i_irdy_b o_irdy_b en_irdy i_devsel_b o_devsel_b en_devsel i_trdy_b o_trdy_b en_trdy i_stop_b o_stop_b en_stop i_par o_par en_par i_perr_b o_perr_b en_perr i_serr_b i_req_b1 to i_req_b7 o_gnt_b1 to o_gnt_b7 i_srst_b i_cpu_cs0_b i_cpu_cs1_b i_cpu_cs2_b i_cpu_adr0 to i_cpu_adr19 i_cpu_data0 to i_cpu_data31 o_cpu_data0 to o_cpu_data31 en_cpu_data i_cpu_be_b0 to i_cpu_be_b3 i_cpu_we_b i_cpu_oe_b o_cpu_wait_b o_pcihost_int i_mode16 o_holdreq_b i_holdack_b i_sdclk o_sd_data0 to o_sd_data31 i_sd_data0 to i_sd_data31 en_sd_data0, en_sd_data1 o_sd_dqm_b0 to o_sd_dqm_b3 o_sd_adr1 to o_sd_adr25 o_sd_cke o_sd_cs_b o_sd_ras_b o_sd_cas_b o_sd_wr_b en_sd_ctl external bus interface pci bus interface sdram bus interface
chapter 3 specifications of pci host bridge macro application note u17121ej1v1an 33 3.3 pin functions the pin functions of each interface are described below. 3.3.1 external bus slave interface pins pin name i/o function active i_srst_b input system reset input low i_cpu_cs0_b input pci host bridge register chip select input low i_cpu_cs1_b input pci i/o area chip select input low i_cpu_cs2_b input pci memory area chip select input low i_cpu_adr0 to i_cpu_adr19 input cpu address input ? i_cpu_data0 to i_cpu_data31 input cpu data input ? o_cpu_data0 to o_cpu_data31 output cpu data output ? en_cpu_data output cpu data output enable output high i_cpu_be_b0 to i_cpu_be_b3 input cpu data byte enable input ? i_cpu_we_b input cpu write data enable input low i_cpu_oe_b input cpu read data output enable input low o_cpu_wait_b output cpu data wait output low o_pcihost_int output pci host bridge interrupt output low i_mode16 input cpu data bus width select input low: 32-bit width high: 16-bit width 3.3.2 sdram bus interface pins pin name i/o function active o_holdreq_b output sdram bus hold request output low i_holdack_b input sdram bus hold acknowledge input low i_sdclk input sdram clock input ? o_sd_data0 to o_sd_data31 output sdram data output ? i_sd_data0 to i_sd_data31 input sdram data input ? en_sd_data0, en_sd_data1 output sdram data enable output low: lower 16 bits (o_sd_data0 to o_sd_data15) high: higher 16 bits (o_sd_data16 to o_sd_data31) o_sd_dqm_b0 to o_sd_dqm_b3 output sdram data mask output low o_sd_adr1 to o_sd_adr25 output sdram address output ? o_sd_cke output sdram clock enable output high o_sd_cs_b output sdram chip select output low o_sd_ras_b output sdram row address strobe output low o_sd_cas_b output sdram column address strobe output low o_sd_wr_b output sdram read/write output low en_sd_ctl output sdram control signal output enable output (output buffer enable of o_sd_adr1 to o_sd_adr25, o_sd_cke, o_sd_cs_b, o_sd_ras_b, o_sd_cas_b, and o_sd_wr_b pins) high
chapter 3 specifications of pci host bridge macro application note u17121ej1v1an 34 3.3.3 pci bus interface pins pin name i/o function active i_pclk input pci clock input ? o_pcirst_b output pci reset output low i_ad0 to i_ad31 input pci address/data input ? o_ad0 to o_ad31 output pci address/data output ? en_ad output pci address/data output enable output (output buffer enable of o_ad0 to o_ad31) high i_cbe0 to i_cbe3 input pci command/byte enable input low o_cbe0 to o_cbe3 output pci command/byte enable output low en_cbe output pci command/byte enable output enable output (output buffer enable of o_cbe0 to o_cbe3) high i_frame_b input pci frame input low o_frame_b output pci frame output low en_frame output pci frame output enable output (output buffer enable of o_frame_b) high i_irdy_b input pci initiator ready input low o_irdy_b output pci initiator ready output low en_irdy output pci initiator ready output enable output (output buffer enable of o_irdy_b) high i_devsel_b input pci device select input low o_devsel_b output pci device select output low en_devsel output pci device select output enable output (output buffer enable of o_devsel_b) high i_trdy_b input pci target ready input low o_trdy_b output pci target ready output low en_trdy output pci target ready output enable output (output buffer enable of o_trdy_b) high i_stop_b input pci stop input low o_stop_b output pci stop output low en_stop output pci stop output enable output (output buffer enable of o_stop_b) high i_par input pci parity input ? o_par output pci parity output ? en_par output pci parity output enable output (output buffer enable of o_par) high i_perr_b input pci parity error input low o_perr_b output pci parity error output low en_perr output pci parity error output enable output (output buffer enable of o_perr_b) high i_serr_b input pci system error input low i_req_b1 to i_req_b7 input pci request input low o_gnt_b1 to o_gnt_b7 output pci grant output low
chapter 3 specifications of pci host bridge macro application note u17121ej1v1an 35 3.4 registers the registers of the pci host bridge macro are listed below. the bit width of all registers is 32 bits. the offset address of each register is the offset value from the base address in the area in which the i_cpu_cs0_b pin becomes active. offset address register name r/w function 00h pci_config_data r/w pci configuration register access data setting 04h pci_config_add r/w pci configuration register access address setting 08h pci_control r/w pci bus control 0ch reserved 10h pci_io_base r/w sets base address of pci bus i/o space accessed from pci i/o area on cpu memory map 14h pci_mem_base r/w sets base address of pci bus memory space accessed from pci memory area on cpu memory map 18h pci_int_ctl r/w pci error interrupt control 1ch pci_err_add r pci error generation address retention 20h to 3fh reserved 40h system_mem_base r/w sets base address of system memory area mapped to pci bus memory space 44h system_mem_range r/w sets range of system memory area mapped to pci bus memory space 48h sdram_ctl r/w sdram access control 4ch to ffh reserved 3.4.1 pci_config_data register after reset: undefined r/w offset address: 00h 31 0 cdata bit name r/w function cdata r/w pci configuration register write access is executed by writing data to this field, and the data written to this field is written to the access target register. pci configuration register read access is executed by reading this field, and the data of the access target register is read.
chapter 3 specifications of pci host bridge macro application note u17121ej1v1an 36 3.4.2 pci_config_add register after reset: 00000000h r/w offset address: 04h 31 0 cadd bit name r/w function cadd r/w sets pci configuration register address of access target. (1) how to set pci_config_add register (a) type 0 (pci device) 31 11 10 8 7 2 1 0 0 0 idsel specification function number register number idsel specification: selects the idsel signal corresponding to the access target pci device. because this pci host bridge macro uses the ad31 to ad11 signals as the idsel signal for each pci device, the ad signal connected to the idsel pin of each pci device is specified in this field. for exam ple, if the ad31 signal is connected to the idsel pin of a pci device, access is enabled by setting bit 31 of cadd to 1. function number: specifies the function number for a multifunction device. register number: specifies the number of t he access target pci configuration register. (b) type 1 (pci-pci bridge) 31 24 23 16 15 11 10 8 7 2 1 0 0 1 bus number device number function number register number bus number: specifies the number of the pci bus connected to the access target pci device. device number: specifies the device nu mber of the access target pci device. function number: specifies the function number for a multifunction device. register number: specifies the number of t he access target pci configuration register.
chapter 3 specifications of pci host bridge macro application note u17121ej1v1an 37 (2) how to access pci configuration register ? write access set the access target register address to the pci_config_add register write the access target register setti ng value to the pci_config_data register ? read access set the access target register address to the pci_config_add register read the pci_config_data register 3.4.3 pci_control register after reset: 07000100h r/w offset address: 08h 31 24 23 17 16 15 8 7 5 4 3 2 1 0 pci_parkcnt 0 0 0 0 0 0 0 pci_bpmode pci_req 0 0 0 pci_reset 0 target_en mem_en io_en bit name r/w function pci_parkcnt r/w sets the time for shifting to bus parking. at the default value, bus parking is performed sev en clocks after the bus status becomes idle. the counter is started when frame# = high and irdy# = high. pci_bpmode r/w sets the bus parking master. 0: limited to this macro 1: master accessed last pci_req r/w enables/disables the req# signal (i_req_b1 to i_req_b7 pins) from the bus master. bit 0 of this field (bit 8 of the pci_control register) is assigned to the pci host bridge macro, and is always 1. 0: disabled 1: enabled pci_reset r/w sets the reset status of the pci bus. 0: reset status 1: reset released target_en r/w sets the operation of the pci bus target of the pci host bridge macro. 0: do not respond to main memory (sdram) access from the pci device 1: respond to main memory (sdram) access from the pci device mem_en r/w enables/disables access from the cpu to the pci memory area. 0: access disabled 1: access enabled io_en r/w enables/disables access from the cpu to the pci i/o area. 0: access disabled 1: access enabled
chapter 3 specifications of pci host bridge macro application note u17121ej1v1an 38 3.4.4 pci_io_base register when i/o accessing the pci bus i/o space via the pci i/o area (area in which the i_cpu_cs1_b pin becomes active: 64 kb), any area of the 4 gb pci bus i/o space can be accessed by setting this register. after reset: 00000000h r/w offset address: 10h 31 1615 0 io_base 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit name r/w function io_base r/w sets the higher 16 bits (bits 16 to 31) of the pci bus i/o space base address when accessing the pci i/o area (area in which the i_cpu_cs1_b pin becomes active) from the cpu. 3.4.5 pci_mem_base register when memory accessing the pci bus memory space via the pci memory area (area in which the i_cpu_cs2_b pin becomes active: 1 mb), any area of the 4 gb pci bus memory space can be accessed by setting this register. however, because the main memory (sdram) is mapped on the pci bus memo ry space, do not overlap the area set by the system_mem_base register and syst em_mem_range register described later. after reset: 80000000h r/w offset address: 14h 31 20 19 0 m_base 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit name r/w function m_base r/w sets the higher 12 bits (bits 20 to 31) of t he pci bus memory space base address when accessing the pci memory area (area in which the i_cpu_cs2_b pin becomes active) from the cpu.
chapter 3 specifications of pci host bridge macro application note u17121ej1v1an 39 3.4.6 pci_int_ctl register the pci_int_ctl register shows the interrupt sources of the pci bus error interrupt (o_pcihost_int) and controls masking and clearin g of these interrupts. this function is used only for debugging and is not used in normal operation. after reset: 000x0f00h r/w offset address: 18h 31 20 19 18 17 16 15 12 11 10 9 8 7 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 clr_serr clr_perr clr_mab clr_tab 0 0 0 0 msk_serr msk_perr msk_mab msk_tab 0 0 0 0 serr perr mabort tabort bit name r/w function clr_serr w clears the pci bus system error (serr# reception) interrupt. 1: cleared clr_perr w clears the pci bus parity error (perr# reception) interrupt. 1: cleared clr_mab w clears the pci bus master abort interrupt. 1: cleared clr_tab w clears the pci bus target abort interrupt. 1: cleared msk_serr r/w sets the mask status of the pci bus system error (serr# reception) interrupt. 0: not masked 1: masked msk_perr r/w sets the mask status of the pci bus pa rity error (perr# reception) interrupt. 0: not masked 1: masked msk_mab r/w sets the mask status of the pci bus master abort interrupt. 0: not masked 1: masked msk_tab r/w sets the mask status of the pci bus target abort interrupt. 0: not masked 1: masked serr r detects the occurrence status of a pci bus system error (serr# reception). 1: system error occurred perr r detects the occurrence status of the pci bus parity error (perr# reception). 1: parity error occurred mabort r detects the occurrence status of the pci bus master abort. 1: master abort occurred tabort r detects the occurrence status of the pci bus target abort. 1: target abort occurred
chapter 3 specifications of pci host bridge macro application note u17121ej1v1an 40 3.4.7 pci_err_add register the pci_err_add register retains the pci bus address when the following errors occur. ? system error (serr# reception) ? parity error (perr# reception) ? master abort ? target abort when the pci_err_add register is read, all the bits are cleared. once an error occurs and a value is set to the pci_err_add register, the first value is retained until r ead access is performed or a new error occurs and the value is updated. this function is used only for debugging and is not used in normal operation. after reset: 00000000h r offset address: 1ch 31 0 err_adr bit name r/w function err_adr r retains the address when a pci bus error occurs.
chapter 3 specifications of pci host bridge macro application note u17121ej1v1an 41 3.4.8 system_mem_base register when the main memory is accessed from the pci device by setting the system_mem_base register and system_mem_range register, the register resp onds to an access of a matching address. after reset: 00000000h r/w offset address: 40h 31 1615 0 s_base 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit name r/w function s_base r/w sets the higher 16 bits (bits 16 to 31) of the ba se address on the pci bus memory space in which the main memory (sdram) is mapped. 3.4.9 system_mem_range register after reset: 0000ffffh r/w offset address: 44h 31 1615 0 s_range 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 bit name r/w function s_range r/w sets the range of the pci bus memory space in which the main memory (sdram) is mapped. it can be set in 64 kb units. 0000h: 64 kb 0001h: 128 kb : 000fh: 1 mb : 00ffh: 16 mb : 0fffh: 256 mb : ffffh: 4 gb
chapter 3 specifications of pci host bridge macro application note u17121ej1v1an 42 3.4.10 sdram_ctl register after reset: 00070230h r/w offset address: 48h 31 24 23 16 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 cycle_latency 0 0 0 bus_size 0 0 cas_latency 0 0 wait_state 0 0 column_size bit name r/w function cycle_latency r/w sets the latency for successive main memory (sdram) accesses from the pci device. a latency of up to 7,650 ns can be set. 00h: no latency 01h: 1 pci clock (30 ns) : ffh: 255 pci clocks (7,650 ns) bus_size r/w sets the bit width of the data bus. 0: 16-bit width 1: 32-bit width cas_latency r/w sets the cas latency. 00: setting prohibited 01: 1 10: 2 11: 3 wait_state r/w sets the wait interval of act cmd, pre act, and cmd act. 00: setting prohibited 01: 1 clock 10: 2 clocks 11: 3 clocks column_size r/w sets the bit width of the column address. 00: 8-bit width 01: 9-bit width 10: 10-bit width 11: 11-bit width
chapter 3 specifications of pci host bridge macro application note u17121ej1v1an 43 the correspondence between the output address signals when the main memory (sdram) is accessed and the pci bus address signals is shown below. table 3-1. row address output correspondence between pci bus address signal and main memory (sdram) address pins (o_sd_adr1 to o_sd_adr25) column_size field setting value 25 to 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 00 (8 bits) 25 to 18 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 01 (9 bits) 25 to 18 17 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 10 (10 bits) 25 to 18 17 16 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 11 (11 bits) 25 to 18 17 16 15 25 24 23 22 21 20 19 18 17 16 15 14 13 12 table 3-2. column address output (precharge command) correspondence between pci bus address signal and main memory (sdram) address pins (o_sd_adr1 to o_sd_adr25) bus_size bit setting value 25 to 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (16 bits) 25 to 18 17 16 15 14 12 11 h 10 9 8 7 6 5 4 3 2 1 1 (32 bits) 25 to 18 17 16 15 14 12 h 11 10 9 8 7 6 5 4 3 2 1 remark h: high level table 3-3. column address output (read/write command) correspondence between pci bus address signal and main memory (sdram) address pins (o_sd_adr1 to o_sd_adr25) bus_size bit setting value 25 to 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (16 bits) 25 to 18 17 16 15 14 12 11 l 10 9 8 7 6 5 4 3 2 1 1 (32 bits) 25 to 18 17 16 15 14 12 l 11 10 9 8 7 6 5 4 3 2 1 remark l: low level
chapter 3 specifications of pci host bridge macro application note u17121ej1v1an 44 3.5 address map the address maps of the cpu memory space and pci bus i/o or memory space are shown below. figure 3-3. cpu memory space/pci bus i/o space address map pci bus i/o space cpu memory space i_cpu_cs1_b area pci i/o area ffffh 0000h ffff ffffh io_base[31:16] + ffffh io_base[31:16] + 0000h 0000 0000h 64 kb pci bus i/o space 64 kb figure 3-4. cpu memory space/pc i bus memory space address map pci bus memory space cpu memory space i_cpu_cs2_b area main memory (sdram) area main memory space pci memory area fffffh 00000h ffff ffffh m_base[31:16] + fffffh m_base[31:16] + 00000h s_base[31:16] + s_range[31:16] + ffffh s_base[31:16] + s_range[31:16] + 0000h 0000 0000h 1 mb pci memory space 1 mb o_sd_cs_b output when accessing from pci host bridge
chapter 3 specifications of pci host bridge macro application note u17121ej1v1an 45 3.6 initializing pci host bridge macro the pci host bridge macro must be initialized accordin g to the following procedure to acknowledge memory access and i/o access to the pci bus and main memory (sdram) access from the pci device. figure 3-5. initializing pci host bridge macro internal pci bus reset released pci_control register set pci_reset bit to 1 main memory (sdram) area setting pci bus control setting pci i/o area setting pci memory area setting pci_mem_base register set any address to m_base field pci_i/o_base register set any address to i/o_base field pci_control register set mem_en and io_en bits to 11 sdram_ctl register set bit width of column address to column_size field set number of wait clocks to wait_state field set cas latency to cas_latency field set bus_size bit to bit width of data bus set latency between successive accesses to cycle_latency field system_mem_base register set any address to s_base field system_mem_range register set any value to s_range field pci_control register set target_en bit to 1 set required bit of pci_req field to 1 sdram control setting
chapter 3 specifications of pci host bridge macro application note u17121ej1v1an 46 3.7 bus width of external bus interface the operation mode of the data bus with respect to the external bus interface can be changed via the i_mode16 pin status. cautions 1. do not change the status of the i_mode16 pin during operation. 2. the i_mode16 pin can only be used to ch ange the operation mode of the data bus with respect to the external bus slave interface. to change the data bus width of the sdram bus interface, use the bus _size bit in 3.4.10 sdram_ctl register. 3. the setting of the i_mode16 pin should correspond with the external bus interface operation mode of the cpu. 4. when 16-bit mode is set, the access cycle is divided for 32-bit access on the external bus interface. accordingly, access is divided similarly on the pci bus interface. therefore, when 16-bit mode is set, because a 32-bit access cycle is not generated on the pci bus interface, a pci device whose register s are only valid for 32-bi t access cannot be accessed. table 3-4. i_mode16 pin status and operation mode of data bus i_mode16 pin data bus operation mode remark low level 32-bit mode 32-bit data bus high level 16-bit mode 16-bit data bus
chapter 3 specifications of pci host bridge macro application note u17121ej1v1an 47 3.8 timing the timing for each interface of the pci host bridge macro is shown below. 3.8.1 external bus interface timing cpu write/cpu read access is performed from the cpu using the bus interface (figures 3-6 and 3-7). when accessing sdram from the pci host bridge macro, bus hold is performed and the main memory is write/read accessed (figures 3-8 to 3-10). figure 3-6. cpu write access i_cpu_csx_b i_cpu_we_b i_cpu_wait_b i_cpu_adr0 to i_cpu_adr19 i_cpu_data0 to i_cpu_data31 i_cpu_be_b0 to i_cpu_be_b3 i_pclk valid valid 1111 1111 0000 remark x = 0 to 2 figure 3-7. cpu read access i_pclk i_cpu_csx_b i_cpu_oe_b i_cpu_wait_b i_cpu_adr0 to i_cpu_adr19 i_cpu_data0 to i_cpu_data31 en_cpu_data i_cpu_be_b0 to i_cpu_be_b3 1111 1111 0000 valid valid remark x = 0 to 2
chapter 3 specifications of pci host bridge macro application note u17121ej1v1an 48 figure 3-8. hold request/hold acknowledge i_sdclk o_holdreq_b i_holdack_b en_sd_ctl sdram control signal output figure 3-9. main memory (sdram) write access (8-burst) i_sdclk o_holdreq_b i_holdack_b o_sd_cs_b o_sd_ras_b o_sd_cas_b o_sd_wr_b o_sd_dqm_b0 to o_sd_dqm_b3 o_sd_data0 to o_sd_data31 o_sd_adr1 to o_sd_adr25 1111 1111 ra wd0 wd1 ca1 ca0 ca2 ca3 ca4 ca5 ca6 ca7 wd2 wd3 wd4 wd5 wd6 wd7 remark sdram_ctl register wait_state field = 10, cas_latency field = 10
chapter 3 specifications of pci host bridge macro application note u17121ej1v1an 49 figure 3-10. main memory (sdram) read access (8-burst) i_sdclk o_holdreq_b i_holdack_b o_sd_cs_b o_sd_ras_b o_sd_cas_b o_sd_wr_b o_sd_dqm_b0 to o_sd_dqm_b3 i_sd_data0 to i_sd_data31 o_sd_adr1 to o_sd_adr25 1111 1111 ra rd0 rd1 ca1 ca0 ca2 ca3 ca4 ca5 ca6 ca7 rd2 rd3 rd4 rd5 rd6 rd7 0000 remark sdram_ctl register wait_state field = 10, cas_latency field = 10
chapter 3 specifications of pci host bridge macro application note u17121ej1v1an 50 3.8.2 pci bus interface timing the pci host bridge macro supports the following pci bus interface timing. (1) pci bus master cycle timing the timing of access from the cpu to the pci device is shown below. (a) configuration read/write cycle, i/o read /write cycle, and memory read/write cycle (i) read cycle timing type: configuration re gister read, internal i/o register read, memory read figure 3-11. read cycle ad h devsel# trdy# frame# stop# irdy# pciclk (ii) write cycle timing type: configurat ion register write, internal i/o register write, memory write figure 3-12. write cycle ad h devsel# trdy# frame# stop# irdy# pciclk
chapter 3 specifications of pci host bridge macro application note u17121ej1v1an 51 (b) target abort cycle timing type: target abort figure 3-13. target abort cycle ad h devsel# trdy# frame# stop# irdy# pciclk (c) master abort cycle timing type: master abort cycle figure 3-14. master abort cycle ad h h h devsel# trdy# pa r frame# stop# irdy# pciclk
chapter 3 specifications of pci host bridge macro application note u17121ej1v1an 52 (d) data parity error timing type: single read & write cycle data parity error figure 3-15. data parity error ad devsel# trdy# pa r frame# stop# irdy# pciclk perr# h (2) pci bus slave cycle timing the timing of access from the pci device to sdram is shown below. (a) memory single read cycle timing type: memory single read cycle figure 3-16. single read cycle ad devsel# trdy# req# frame# stop# irdy# pciclk gnt#
chapter 3 specifications of pci host bridge macro application note u17121ej1v1an 53 (b) memory single write cycle timing type: memory single write cycle figure 3-17. single write cycle ad devsel# trdy# req# frame# stop# irdy# pciclk gnt# (c) burst read cycle timing type: memory burst read cycle ? not disconnect figure 3-18. burst read cycle ad 0 1 2 3 4 5 6 7 devsel# trdy# req# frame# stop# irdy# pciclk gnt# h
chapter 3 specifications of pci host bridge macro application note u17121ej1v1an 54 (d) burst write cycle timing type: memory burst write cycle ? not disconnect figure 3-19. burst write cycle ad 0 1 2 3 4 5 6 7 devsel# trdy# req# frame# stop# irdy# pciclk gnt# h (e) abort cycle timing type: target abort cycle & master abort cycle figure 3-20. abort cycle ad devsel# trdy# req# frame# stop# irdy# pciclk gnt# serr# h
chapter 3 specifications of pci host bridge macro application note u17121ej1v1an 55 (f) data parity error (i) read data parity error 1 timing type: single read cycle data parity error figure 3-21. read data parity error ad devsel# trdy# pa r frame# stop# irdy# pciclk perr# h (ii) read data parity error 2 timing type: burst read cycle data parity error figure 3-22. read data parity error 2 ad devsel# trdy# pa r frame# stop# irdy# pciclk perr#
chapter 3 specifications of pci host bridge macro application note u17121ej1v1an 56 (iii) write data parity error 1 timing type: single writ e cycle data parity error figure 3-23. write data parity error 1 ad devsel# trdy# pa r frame# stop# irdy# pciclk perr# h serr# (iv) write data parity error 2 timing type: burst write cycle data parity error figure 3-24. write data parity error 2 ad devsel# trdy# pa r frame# stop# irdy# pciclk perr# serr#
application note u17121ej1v1an 57 chapter 4 configuration examples of fpga integration this chapter describes configuration examples in whic h the pci host bridge macro is integrated in an fpga (altera?s ep20k200eqc240-1x). 4.1 conditions for configurati on examples of fpga integration the conditions in the configur ation examples are as follows. (1) cpu: v850e/me2 (2) bus width of external bus interface: 32 bits (3) cs space of pci host bridge: csz6 (4) cs space of sdram: csz3 (5) sdram: connecting two 16 m 16 sdrams (4 m 16 4 banks) (6) pci connection: 2 devices 4.2 points to remember when creating top layer of fpga points to remember when integrating the pci host bridge macro with an fpga are indicated below. (1) first decode the chip select from the address before creation. ? i_cpu_cs0_b: pci host bridge register chip select (offset address in 3.4 registers ) ? i_cpu_cs1_b: pci i/o area chip select (see figure 3-3 cpu memory space/pci bus i/o space address map ) ? i_cpu_cs2_b: pci memory area chip select (see figure 3-4 cpu memory space/pci bus memory space address map ) (2) because the buffers of the address bus and data bus for the expansion bus interface are output when the pci host bridge controls sdram, they become bidirectional pins via the selector. the following pins that contro l sdram become 3-state output. ? dqm0 to dqm3, sdcke, sdcs, sdras, sdcas, sdwez (3) the following pci bus interface pins become bidirectional pins. ? ad, cbe, frame, irdy, devsel, trdy, stop, par, perr (4) there are three interrupt request output signals: one is output from the pci host bridge; the remaining two are inta and intb signals from the external pci slot and are directly connected to the cpu.
chapter 4 configuration examples of fpga integration application note u17121ej1v1an 58 4.3 reference diagram for fpga top connection the reference diagram for connecting the pci host bridge macro with the fpga top layer is shown below. internal h fixed input fpga top i_pclk i_cpu_we_b pclk o_pcirst_b pcirst en_ad i_cpu_cs0_b i_cpu_cs1_b i_cpu_cs2_b ra21 to ra25 i_cpu_oe_b o_cpu_wait_b i_holdack_b i_sdclk en_sdclk i_cpu_adr0 o_gnt_b2 o_pcihost_in o_gnt_b1 gnt2 intb int2 inta gnt1 o_holdreq_b i_ad0 to i_ad31 o_ad0 to o_ad31 ad0 to ad31 en_cbe i_cbe0 to i_cbe3 o_cbe0 to o_cbe3 i_cpu_adr1 to i_cpu_adr19 o_sd_adr1 to o_sd_adr25 cbe0 to cbe3 o_sd_dqm_b0 to o_sd_dqm_b3 o_sd_cke o_sd_cs_b o_sd_ras_b o_sd_cas_b o_sd_wr_b en_sd_ctl i_sd_data0 to i_sd_data31 o_cpu_data0 to o_cpu_data31 o_sd_data0 to o_sd_data31 en_cpu_data i_cpu_be_b0 to i_cpu_be_b3 i_cpu_data0 to i_cpu_data31 i_req_b1 req1 o_gnt_b3 to o_gnt_b7 en_frame i_frame_b o_frame_b frame i_serr_b serr i_req_b2 req2 i_req_b3 to i_req_b7 en_irdy i_irdy_b o_irdy_b irdy en_devsel i_devsel_b o_devsel_b devsel en_trdy i_trdy_b o_trdy_b trdy en_stop i_stop_b o_stop_b stop en_par i_par o_par par en_perr i_perr_b o_perr_b perr open open pci host bridge macro address decoder selector en_sd_data0, en_sd_data1 int1 int0 sdwez sdcasz sdcs sdcke hldrqz waitz dqm0 to dqm3 sdclk hldakz rdz wrz0 benz0 to benz3 ra0 csz6 i_srst_b vbresetz rd0 to rd31 ra1 to ra25 sdrasz
chapter 4 configuration examples of fpga integration application note u17121ej1v1an 59 4.4 fpga top pin functions the pin information when integrating the pci hos t bridge macro with an fpga is shown below. 4.4.1 cpu bus slave interface pins pin name i/o function vbresetz input system reset input csz6 input pci host bridge chip select input ra0 to ra25 i/o cpu address i/o rd0 to rd31 i/o cpu data i/o benz0 to benz3 input cpu data byte enable input wrz input cpu data write enable input rdz input cpu data read enable input waitz output cpu data wait output int0 output pci host bridge interrupt output 4.4.2 sdram bus interface pins pin name i/o function hldreqz output sdram bus hold request output hldackz input sdram bus hold acknowledge input sdclk input sdram clock input sdcke output sdram clock enable output sdcs output sdram chip select output sdrasz output sdram row address strobe output sdcasz output sdram column address strobe output sdwez output sdram read/write output dqm0 to dqm3 output sdram output disable output
chapter 4 configuration examples of fpga integration application note u17121ej1v1an 60 4.4.3 pci bus interface pins pin name i/o function pclk input pci clock input pcirst output pci reset output ad0 to ad31 i/o pci address/data i/o cbe0 to cbe3 i/o pci command/byte enable i/o frame i/o pci frame i/o irdy i/o pci initiator ready i/o devsel i/o pci device select i/o trdy i/o pci target ready i/o stop i/o pci stop i/o par i/o pci parity i/o perr i/o pci parity error i/o serr input pci system error input req1, req2 input pci request input gnt1, gnt2 output pci grant output int1, int2 output pci inta, intb output
chapter 4 configuration examples of fpga integration application note u17121ej1v1an 61 4.5 fpga top pin configuration the connection diagram of the pci host bridge macro pins in an fpga is shown below. 4.5.1 internal connection di agram of external bus interface i_srst_b pci host bridge macro fpga top i_cpu_cs0_b i_cpu_cs1_b i_cpu_cs2_b i_cpu_we_b i_cpu_adr1 to i_cpu_adr19 i/o buffer a1 to a25 reset cs6 vbresetz cs6 ra0 ra1 to ra25 external bus interface a0 selector address decoder o_sd_adr1 to o_sd_adr25 i_cpu_data0 to i_cpu_data31 i_sd_data0 to i_sd_data31 o_cpu_data0 to o_cpu_data31 o_sd_dqm_b0 to o_sd_dqm_b3 i_cpu_be_b0 to i_cpu_be_b3 o_sd_data0 to o_sd_data31 i_cpu_oe_b o_sd_wr_b o_cpu_wait_b i_holdack_b i_sdclk o_pcihost_int o_holdrq_b o_sd_cke o_sd_cs_b o_sd_ras_b o_sd_cas_b en_sd_ctl selector en_cpu_data en_sd_data0, en_sd_data1 i_srst_b rdz rd wrz d0 to d31 rd0 to rd31 dqm0 to dqm3 benz0 to benz3 xxbe/xxdqm we/wr waitz wait int0 intp10 hldrqz hldrq hldakz hldak sdcasz sdcas sdclk busclk sdcke sdcke sdcsz cs3 sdrasz sdras
chapter 4 configuration examples of fpga integration application note u17121ej1v1an 62 4.5.2 internal connection diagram of pci bus interface i/o buffer h fixed fpga top pci bus i_pclk o_pcirst_b en_ad o_gnt_b1, o_gnt_b2 i_ad0 to i_ad31 o_ad0 to o_ad31 en_cbe i_cbe0 to i_cbe3 o_cbe0 to o_cbe3 i_req_b1, i_req_b2 i_req_b3 to i_req_b7 o_gnt_b3 to o_gnt_b7 en_frame i_frame_b o_frame_b clk pclk i_serr_b serr# serr c/be0# to c/be3# cbe0 to cbe3 pcirst rst# ad0 to ad31 ad0 to ad31 frame frame# en_irdy i_irdy_b o_irdy_b irdy irdy# en_devsel i_devsel_b o_devsel_b devsel devsel# en_trdy i_trdy_b o_trdy_b trdy trdy# en_stop i_stop_b o_stop_b stop stop# en_par i_par o_par par par gnt1#, gnt2# gnt1, gnt2 req1#, req2# req1, req2 en_perr i_perr_b o_perr_b perr perr# open pci host bridge macro
chapter 4 configuration examples of fpga integration application note u17121ej1v1an 63 4.5.3 external connection diagram of external bus interface (example of connection with v850e/me2) vbresetz system reset fpga (pci host bridge) sdram1 sdram2 ra2 to ra14 ra24, ra25 rd0 to rd31 benz0 to benz3 wrz sdcke sdcs sdrasz sdcasz sdclk rdz waitz int0 hldrqz hldakz reset v850e/me2 hldak hldrq intpxxx wait rd a0 to a22 a24, a25 d0 to d31 xxbe/xxdqm wr/we sdcke csx sdras sdcas busclk a0 to a12 ba0, ba1 dq0 to dq31 dqm0, dqm1 /we cke /cs /ras /cas clk dqm2, dqm3 remarks 1. this is an example using two sdrams of 4 m words 16 bits 4 banks (row address: 13 bits, column address: 9 bits). 2. xx: ll, lu, ul, uu
chapter 4 configuration examples of fpga integration application note u17121ej1v1an 64 4.5.4 external connection diagram of pci bus interface pci device clk pclk pci bus clock pci host bridge pci device 1 ad00 to ad31 cbe0 to cbe3 pcirst frame irdy devsel trdy stop par perr serr req1 gnt1 ad00 to ad31 idsel note c/be0# to c/be3# rst# frame# irdy# devsel# trdy# stop# par perr# serr# req# gnt# clk ad00 to ad31 idsel note c/be0# to c/be3# rst# frame# irdy# devsel# trdy# stop# par perr# serr# req# gnt# req2 gnt2 note connect one of the ad31 to ad11 signals to the idsel pin of each pci device.
chapter 4 configuration examples of fpga integration application note u17121ej1v1an 65 4.6 cautions on designing fpga cautions when fitting an fpga using altera?s ?quartusll design software? are shown below. 4.6.1 fpga fitting design (1) set the ?i/o standard? buffer type to ?3.3-v pci? for the following pci bus interface pins. pin name/usage dir i/o standard inta input 3.3-v pci intb input 3.3-v pci frame bidir 3.3-v pci devsel bidir 3.3-v pci req1 input 3.3-v pci req2 input 3.3-v pci gnt1 output 3.3-v pci gnt2 output 3.3-v pci irdy bidir 3.3-v pci trdy bidir 3.3-v pci stop bidir 3.3-v pci pcirst output 3.3-v pci ad0 to ad31 bidir 3.3-v pci cbe0 to cbe3 bidir 3.3-v pci par bidir 3.3-v pci perr bidir 3.3-v pci serr input 3.3-v pci (2) determine the pin assignment taking equal length wiri ng into consideration for the pci bus interface pins. (3) specify the ?pclk? and ?sdclk? signals as global clk. 4.6.2 pci bus interface timing parameters (as constraint of pci clk = 33 mhz) adjust the timing so that the following pc i specification values are satisfied. (1) input setup time to clk point to point pin setup hold req1, req2 10 ns 0 ns other pci pins 7 ns 0 ns
chapter 4 configuration examples of fpga integration application note u17121ej1v1an 66 (2) clk to signal valid delay signals pin min. max. all pci pins 2 ns 11 ns the following specification values apply to the pci bus timing (pci clk = 33 mhz). figure 4-1. output timing clk t val output delay figure 4-2. input timing clk t h t su input inputs valid table 4-1. 33 mhz timing parameters symbol parameter min. (ns) max. (ns) t val clk to signal valid delay bused signals 2 11 t val (ptp) clk to signal valid delay point to point signals 2 12 t su input setup time to clk bused signals 7 t su (ptp) input setup time to clk point to point signals 10 t h input hold time from clk 0 4.6.3 sdram interface timing the timing for interfacing with sdram depends on the ex ternal bus interface and the sdram to be connected. adjust the timing to suit the system.
application note u17121ej1v1an 67 chapter 5 application examples this chapter introduces the configurat ion of an evaluation board that mounts the v850e/me 2, as well as program examples. this is an example of an application used to operate a hdd with an ide controller mounted on the pci connecter. 5.1 block diagram of evaluation board a block diagram of the evaluation board is shown below. figure 5-1. block diagra m of evaluation board pci host evaluation board memc bus memc bus pci bus pci bus pci host bridge macro pci connector hard disk drive pci-ide controller flash memory 7-segment/ sw v850e/me2 (176-pin lqfp) sram (1 mb) sdram (64 mb) rom socket (for emulation) n-wire connector pci connector
chapter 5 application examples application note u17121ej1v1an 68 5.2 specifications of evaluation board the specifications of the ev aluation board are as follows. table 5-1. specifications of evaluation board item description cpu v850e/me2 cpu operating frequency 30 mhz memc bus operating frequency 30 mhz evaluation board memory flash memory csz0 area (32-bit width): 8 mb sram csz1 area (32-bit width): 1 mb sdram csz3 area (32-bit width): 64 mb evaluation board peripheral i/o pci host bridge csz6 area (32-bit width): pci rev.2.1 compliant host interface (33 mhz) other 7-segment display 7-segment display 2 can be controlled by v850e/me2 general-purpose port the device numbers of the pci bus are assigned as follows. table 5-2. idsel connection slot device number remark pci slot 1 (j2) ad31 connect ad31 to idsel pci slot 2 (j3) ad30 connect ad30 to idsel
chapter 5 application examples application note u17121ej1v1an 69 5.3 example of evaluation board connection circuit a circuit example of connection of the v850e/me2 with sdram, fpga, and a pci device (slot) is shown below. figure 5-2. example of evaluation board connection circuit reset system reset pci bus clock cs6 cs3 rd rd wait int0 int1 int2 hldrq hldak busclk sdcke sdras sdcas we xxbe xxwr a0 to a25 v850e/me2 a0 to a12 ba0, ba12 d0 to d31 clk ras cas we cke cs dqm0, dqm1 dqm2, dqm3 sdram sdram csz6 vbestz ra0 to ra25 rd0 to rd25 benz0 to benz3 wrz0 to wrz3 rdz waitz int0 int1 int2 hldrqz hldakz dqm0 to dqm3 sdclk sdcke sdcs sdrasz sdcasz sdwez pclk pcirst irdy devsel trdy stop pa r perr serr req1 gnt1 inta cbe0 to cbe3 frame ad0 to ad31 fpga (pci host bridge) rst# ad0 to ad31 idsel# frame# irdy# devsel# trdy# stop# pa r serr# perr# req# gnt# int# c/be#0 to c/be#3 clk pci device rst# ad0 to ad31 idsel# frame# irdy# devsel# trdy# stop# pa r serr# perr# req# gnt# int# req2 gnt2 intb c/be#0 to c/be#3 clk pci device a24, a25 a2 to a14 remark xx: ll, lu, ul, uu
chapter 5 application examples application note u17121ej1v1an 70 5.4 evaluation board memory space the evaluation board memory space is shown below. figure 5-3. evaluation board memory space 08f ffffh 7ff ffffh cff ffffh 07f ffffh 010 0000h 080 0000h 400 0000h c80 0000h 07f ffffh 000 0000h 080 0000h 400 0000h 3ff 8000h 00f ffffh 3ff 7fffh 3ff afffh csz0 rom area (7 mb) csz1 external sram area (1 mb) csz3 external sram area (64 mb) csz6 pci host bridge area (8 mb) sram area (56 mb) flash memory area (7 mb) access-prohibited area on-chip instruction ram area (1 mb) 3ff b000h 3ff efffh on-chip peripheral i/o mirror (4 kb) sdram area (area 1 = 64 mb) reserved area (area 2 = 64 mb) on-chip data ram mirror (16 kb) 3ff f000h 3ff ffffh fff 8000h fff 7fffh fff afffh access-prohibited area fff b000h fff efffh on-chip peripheral i/o area (4 kb) on-chip data ram area (16 kb) pci host bridge cs area (63.9 mb) fff f000h fff ffffh 800 0000h 7ff ffffh c00 0000h bff ffffh area 0 (64 mb) area 1 (64 mb) area 2 (64 mb) area 3 (64 mb) 256 mb
chapter 5 application examples application note u17121ej1v1an 71 the pci memory i/o space is assigned to the csz6 area. the base address of the pci memory space is set to cc0 0000h. the base address of the pci i/o space is set to c80 0000h. figure 5-4. comparison between cpu memory space and pci memory space pci memory space 0000 0000h ffff ffffh system_mem_base system_mem_base cc0 0000h cff ffffh pci_mem_base[31:22] + 00 0000h pci_mem_base[31:22] + 3f ffffh system_mem_base system_mem_base main memory area (sdram) pci memory area cs6 area (4 mb) cpu memory space main memory area (sdram) pci memory area figure 5-5. comparison between cp u memory space and pci i/o space pci i/o space 0000 0000h ffff ffffh ca0 0000h c80 0000h cbf ffffh pci_mem_base[31:21] + 00 0000h pci_mem_base[31:21] + 1f ffffh pci i/o area (2 mb) cs6 area (4 mb) cpu memory space pci i/o area pci bridge i/o area
chapter 5 application examples application note u17121ej1v1an 72 5.5 sample program examples this sample program is assumed to be used in an environment with the pci-ide board connected to the v850e/me2 evaluation board as the pci device. the pci-ide board is connected to the ide hdd, and the sample program accesses the ide hdd. 5.5.1 development tools (1) multi tm 1.8.9 integrated development environmen t made by green hills software tm , inc. (2) pci-ide board ide card of pci interface connected to evaluation board. used by connecting ide hdd in this application. 5.5.2 program configuration the sample program configuration is shown below. (1) pci host bridge macro init ialization sample program list first the pci host bridge macro must be init ialized for the cpu to access the pci area. the correspondence between the pci memory space and cpu memory space, the interrupts from pci, and access control from the cpu to the pci memory spac e are set by the pci host bridge macro registers. (2) pci configuration space access sample program list when initialization of the pci host bridge macro ends, in itialization of each pci device connected to the pci bus is performed. initialization is performed mainly by setting the configuration s pace registers existing in each pci device. the confi guration space registers can be accessed only by executing a configuration cycle using the pci_config_add and pci_config_data regist ers described in the register descriptions. (3) ide hdd access sample program list when initialization of the pci host bridge macro and pci devices ends, the pci device can actually be operated. the pci device is operated by setting the registers assigned to the configuration space and pci i/o area. the ide bus setting is performed and the ide hdd is actually accessed by operating the pci-ide board registers in this sample code.
chapter 5 application examples application note u17121ej1v1an 73 5.5.3 v850e/me2 pci host bridge macr o initialization sample program list ///////////////////////////////////////////////////////////////// // v850e/me2 - pci host bridge macro initialization sample // // overview: initializes pci host bridge macro by setting // // pci bridge io area register group. // // specific initialization is described in // // function pci_hbm_init(). // // // // pci_hbm_init() is called after functions required for // // accessing host bridge macro, such as cpu and peripheral // // i/o, are initialized. // // // ///////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////// // defines base address of pci area and sdram area. // // start address of pci area is 0c80_0000h, and start address // // of sdram area is 0400_0000h in this application. // ///////////////////////////////////////////////////////////////// #define base_address_me2pciif (0x0c800000) #define base_address_pci_io (base_address_me2pciif) #define base_address_pci_bridge_io (base_address_me2pciif + 0x00200000) #define base_address_pci_mem (base_address_me2pciif + 0x00400000) #define base_address_sdram (0x04000000) #define range_sdram (0x03ffffff) // 64mb //////////////////////////////////////////////////////// // pci host bridge macro register address definition // //////////////////////////////////////////////////////// #define phbmr_pci_config_data (base_address_pci_bridge_io+0x00) #define phbmr_pci_config_add (base_address_pci_bridge_io+0x04) #define phbmr_pci_control (base_address_pci_bridge_io+0x08) #define phbmr_pci_io_base (base_address_pci_bridge_io+0x10) #define phbmr_pci_mem_base (base_address_pci_bridge_io+0x14) #define phbmr_pci_int_ctl (base_address_pci_bridge_io+0x18) #define phbmr_pci_err_add (base_address_pci_bridge_io+0x1c) #define phbmr_system_mem_base (base_address_pci_bridge_io+0x40) #define phbmr_system_mem_range (base_address_pci_bridge_io+0x44) #define phbmr_sdram_ctl (base_address_pci_bridge_io+0x48) /////////////////////////////////////////// // macro definition for register access // /////////////////////////////////////////// #define v850eme2_regw(x) *((volatile unsigned int *)((int)x))
chapter 5 application examples application note u17121ej1v1an 74 ///////////////////////////////////////////////////////////////////////// // function name: pci_hbm_init // // function: initializes pci host bridge macro. // // argument: none // // return value: none // // remark: base addresses of this initialization sample are as follows.// // - base address of pci i/o space: 0c80_0000h // // - base address of pci memory space: 0cc0_0000h // // - base address on pci bus memory space in which // // main memory (sdram) is mapped: 0400_0000h // // - range of pci bus memory space in which // // main memory (sdram) is mapped: 03ff_ffffh // // other settings are required according to system // // requirements and mounting. // ///////////////////////////////////////////////////////////////////////// void pci_hbm_init(void) { v850eme2_regw(phbmr_pci_control) = 0x07000110; // pci_control register // bit 31-24: pci_parkcnt = 1 // (set time for shifting to bus parking to 7) // bit 15-08: pci_req = 1 (enable i_req_b0) // bit 4: pci_reset bit = 1 (release pci bus reset) v850eme2_regw(phbmr_pci_io_base) = base_address_pci_io; // pci_io_base register // set pci i/o space base address to c800000h. v850eme2_regw(phbmr_pci_mem_base) = base_address_pci_mem; // pci_mem_base register // set pci memory space base address to cc00000h. v850eme2_regw(phbmr_pci_control) = 0x07000113; // pci_control register // bit 31-24: pci_parkcnt = 1 // (set time for shifting to bus parking to 7) // bit 15-08: pci_req = 1 (enable i_req_b0) // bit 4: pci_reset bit = 1 (release pci bus reset) // bit 1: pci_mem_en bit = 1 // (enable access from cpu to pci memory area) // bit 0: pci_io_en bit = 1 // (enable access from cpu to pci i/o area) v850eme2_regw(phbmr_system_mem_base) = base_address_sdram; // system_mem_base register // set base address on pci bus memory space in which main // memory (sdram) is mapped to 4000000h.
chapter 5 application examples application note u17121ej1v1an 75 v850eme2_regw(phbmr_system_mem_range) = range_sdram; // system_mem_range register // set range of pci bus memory space in which main // memory (sdram) is mapped to 3ffffffh (64 mb). v850eme2_regw(phbmr_sdram_ctl) = 0x00071211; // sdram_ctl register // bit 23-16: cycle_latency = 07h // (set latency for successive main memory // (sdram) access from pci device to 210 ns) // bit 12: bus_size = 1b // (set bit width of data bus to 32 bits) // bit 09-08: cas_latency = 10b (set cas latency to 2) // bit 05-04: wait_state = 01b // (set wait interval of act cmd, pre act, // and cmd act to 1 clock) // bit 01-00: column_size = 01b // (set bit width of column address to 9 bits) v850eme2_regw(phbmr_pci_control) = 0x07000717; // bit 31-24: pci_parkcnt = 1 // (set time for shifting to bus parking to 7) // bit 15-08: pci_req = 1 (enable i_req_b0) // bit 4: pci_reset bit = 1 (release pci bus reset) // bit 1: pci_mem_en bit = 1 // (enable access from cpu to pci memory area) // bit 0: pci_io_en bit = 1 // (enable access from cpu to pci i/o area) return; } ///////////////////////////////////////////////////////////////// // function name: main // // function: initializes pci host bridge macro. // // argument: none // // return value: 0: normal end // ///////////////////////////////////////////////////////////////// int main(void) { // initializes pci host bridge macro. pci_hbm_init(); return 0; }
chapter 5 application examples application note u17121ej1v1an 76 5.5.4 pci configuration sp ace access sample program list ///////////////////////////////////////////////////////////////////////// // pci configuration space access sample // // overview: configuration space is accessed using procedure // // shown below. // // 1) write 32-bit value indicating pci device, function // // number, and register number to be accessed to // // pci_config_add register of pci host bridge macro. // // 2) when reading configuration space register, read // // (word access) 32-bit value in pci_config_data // // register of pci host bridge macro. // // when writing to configuration space register, write // // (word access) 32-bit value to pci_config_data register // // of pci host bridge macro. // // // // this procedure is combined in functions pci_configread // // and pci_configwrite shown below. // // function pci_config_baseaddressinit uses function // // pci_configwrite to set base address register in // // configuration space. // // // ///////////////////////////////////////////////////////////////////////// ////////////////////// // type declaration // ////////////////////// typedef char byte; typedef short int hword; typedef int word; typedef unsigned char ubyte; typedef unsigned short int uhword; typedef unsigned int uword; typedef volatile unsigned char vubyte; typedef volatile unsigned short int vuhword; typedef volatile unsigned int vuword; ///////////////////////////////////////////////////////////////// // function name: pci_configread // // function: reads 32-bit value in pci configuration space. // // argument: configadd: register address of configuration space// // return value: read configuration space register data // ///////////////////////////////////////////////////////////////// uword pci_configread(uword configadd) { v850eme2_regw(phbmr_pci_config_add) = configadd; return v850eme2_regw(phbmr_pci_config_data); }
chapter 5 application examples application note u17121ej1v1an 77 ///////////////////////////////////////////////////////////////// // function name: pci_configwrite // // function: writes 32-bit value to pci configuration space. // // argument: configadd: register address of configuration space// // configdata: register data of configuration space // // return value: none // ///////////////////////////////////////////////////////////////// void pci_configwrite(uword configadd, uword configdata) { v850eme2_regw(phbmr_pci_config_add) = configadd; v850eme2_regw(phbmr_pci_config_data) = configdata; return; } ///////////////////////////////////////////////////////////////////////// // function name: pci_config_baseaddressinit // // function: sets base address of configuration space. // // argument: none // // return value: none // // details: sets base address register of offset 10h to 24h in // // configuration space of pci device connected to ad30 // // signal by idsel as follows. // // // // ata command register base address (10h) : 0c80_0000h // // ata control register base address (14h) : 0c80_0008h // // bus master control register base address(18h) : 0c80_0010h // // // ///////////////////////////////////////////////////////////////////////// void pci_config_baseaddressinit(void) { uword configaddress; uword configdata; /////////////////////////////////////// // ata command register base address // /////////////////////////////////////// configaddress = 0x40000010; // bit 31-11 : idsel specification = 010000000000000000000b // select pci device connected to ad30 // bit 10-08 : function number = 00b // bit 07-02 : register number = 4 (000100b), // -> ata command register base address // (in the case of pci-ide asic board used in this application) // bit 01-00 : 00b (fixed) pci_configwrite(configaddress, 0x0c800000);
chapter 5 application examples application note u17121ej1v1an 78 /////////////////////////////////////// // ata control register base address // /////////////////////////////////////// configaddress = 0x40000014; // bit 31-11 : idsel specification = 010000000000000000000b // select pci device connected to ad30 // bit 10-08 : function number = 00b // bit 07-02 : register number = 5 (000101b), // -> ata control register base address // (in the case of pci-ide asic board used in this application) // bit 01-00 : 00b (fixed) pci_configwrite(configaddress, 0x0c800008); ////////////////////////////////////////////// // bus master control register base address // ////////////////////////////////////////////// configaddress = 0x40000018; // bit 31-11 : idsel specification = 010000000000000000000b // select pci device connected to ad30 // bit 10-08 : function number = 00b // bit 07-02 : register number = 6 (000110b) // -> bus master control register base address // (in the case of pci-ide asic board used in this application) // bit 01-00 : 00b (fixed) pci_configwrite(configaddress, 0x0c800010); return; } ///////////////////////////////////////////////////////////////// // function name: main // // function: sets base address of configuration space. // // argument: none // // return value: 0: normal end // ///////////////////////////////////////////////////////////////// int main(void) { // initializes pci host bridge macro. pci_hbm_init(); // sets base address of configuration space. pci_config_baseaddressinit(); return 0; }
chapter 5 application examples application note u17121ej1v1an 79 5.5.5 ide hdd access sample program list /////////////////////////////////////////////////////////////////////////////// // ide hdd access sample // // overview: issues ata commands to hdd, which is ata device, via pci-ide // // asic board connected to pci slot of evaluation board. // // ata commands to be issued are as follows. // // // // idle immediate, identify device, set feature, // // read sector(s), write sector(s), read dma, write dma // // // // ata command is executed by executing device selection // // protocol to determine that command is issued to either // // master device or slave device. ata command is issued // // and data is transferred using transfer protocol // // corresponding to each ata command. four transfer // // protocols, pio datain transfer, pio dataout transfer, // // pio nondata transfer, and dma transfer, are available. // // // // this sample program is provided with device selection // // protocol and four transfer protocols as functions. // // corresponding transfer protocol function is called // // from function processing each ata command. // // // /////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////// // pci-ide asic board register address definition // ///////////////////////////////////////////////////// ////////////////////// // ide command area // ////////////////////// #define idereg_data ((vuword*)(base_address_pci_io + 0x00)) #define idereg_error ((vubyte*)(base_address_pci_io + 0x01)) #define idereg_error_err_bit (0x01) #define idereg_features ((vubyte*)(base_address_pci_io + 0x01)) #define idereg_sector_count ((vubyte*)(base_address_pci_io + 0x02)) #define idereg_sector_number ((vubyte*)(base_address_pci_io + 0x03)) #define idereg_cylinder_low ((vubyte*)(base_address_pci_io + 0x04)) #define idereg_cylinder_high ((vubyte*)(base_address_pci_io + 0x05)) #define idereg_device_head ((vubyte*)(base_address_pci_io + 0x06)) #define idereg_status ((vubyte*)(base_address_pci_io + 0x07)) #define idereg_command ((vubyte*)(base_address_pci_io + 0x07)) ////////////////////// // ide control area // //////////////////////
chapter 5 application examples application note u17121ej1v1an 80 #define idereg_alternate_status ((vubyte*)(base_address_pci_io + 0x0e)) #define idereg_device_control ((vubyte*)(base_address_pci_io + 0x0e)) ///////////////////////// // bus master i/o area // ///////////////////////// #define idereg_busmaster_start_stop ((vuword*)(base_address_pci_io + 0x10)) #define idereg_dsctbl_start_address ((vuword*)(base_address_pci_io + 0x14)) #define idereg_interrupt_control ((vuword*)(base_address_pci_io + 0x18)) /////////////////////////// // error code definition // /////////////////////////// #define status_success 0 #define status_timeout_bsy0_drq0 1 #define status_timeout_device_selection 1 #define status_timeout_drdy1 2 #define status_timeout_bsy0 3 #define status_timeout_intrq 4 #define status_timeout_bmend 5 #define status_ide_error(ide_error_reg) (0x10000000 | (uword)(ide_error_reg)) /////////////////////////////////////////////////// // transfer mode timing setting value definition // /////////////////////////////////////////////////// // see ide specifications for details of transfer mode timing setting values shown below. // setting value passed to set_features command in set_transfer_mode() #define pio_mode0 0x08 #define udma_mode0 0x40 // setting value of timing register (when ide operation clock is 33 mhz) #define ide_pio_timing_ide33mhz_mode0 (0x00020906) #define ide_udma_timing1_ide33mhz_mode0 (0x00000202) #define ide_udma_timing2_ide33mhz_mode0 (0x00000005) //////////////////////////// // structure declaration // //////////////////////////// /////////////////////////////////////// // structure for issuing ata command // /////////////////////////////////////// typedef struct{ ubyte features; // features register ubyte sector_count; // sector count register ubyte sector_number; // sector number register
chapter 5 application examples application note u17121ej1v1an 81 ubyte cylinder_low; // cylinder low register ubyte cylinder_high; // cylinder high register ubyte device_head; // device/head register ubyte command; // command register } ata_command; //////////////////////////////////////////// // descriptor table for ultradma transfer // //////////////////////////////////////////// typedef struct{ uword transfer_address; // transfer address uword transfer_byte; // number of transfer bytes uword next_table_address; // next table address } discriptor_table; ///////////////////////////// // initialization function // ///////////////////////////// ///////////////////////////////////////////////////////////////// // function name: pci_config_modeinit // // function: sets initialization of pci-ide asic board. // // argument: none // // return value: none // // details: sets handling of interrupts and errors, coding and // // then resets ide bus. // // // ///////////////////////////////////////////////////////////////// void pci_config_modeinit(void) { uword configaddress; uword configdata; ////////////////////////////// // setting of pci functions // ////////////////////////////// configaddress = 0x40000004; // bit 31-11 : idsel specification = 010000000000000000000b // select pci device connected to ad30 // bit 10-08 : function number = 00b // bit 07-02 : register number = 1 (000001b) // -> status / command // bit 01-00 : 00b (fixed) configdata = 0x02000145; // bit 26-25 : devsel timing = 01b (medium fixed) // bit 8 : serr enable = 1b : output pci_serr. // bit 6 : parity error response = 1b : output pci_serr
chapter 5 application examples application note u17121ej1v1an 82 // when parity error is detected. // bit 2 : bus master = 1b : enable pci bus master transfer // bit 0 : io space = 1b : enable io access to pci-ide asic board pci_configwrite(configaddress, configdata); //////////////////////////// // setting des to disable // //////////////////////////// configaddress = 0x40000058; // bit 31-11 : idsel specification = 010000000000000000000b // select pci device connected to ad30 // bit 10-08 : function number = 00b // bit 07-02 : register number = 22 (010110b), // -> ide bus master control // (in the case of pci-ide asic board used in this application) // bit 01-00 : 00b (fixed) // ide bus master control // disable des (set bit16 des_on to 0) configdata = pci_configread(configaddress); pci_configwrite(configaddress, configdata & 0xfffeffff); /////////////////////////////////////////// // setting of interrupt control register // /////////////////////////////////////////// *idereg_interrupt_control &= 0xfffcffff; // bit 17 : pci bus master end interrupt mask = 0b (interrupt enabled) // bit 16 : pci i/f interrupt mask = 0b (interrupt enabled) //////////////////////////////////////// // setting of device command register // //////////////////////////////////////// *idereg_device_control = 0x00; // bit 2 : nien = 0b (set intrq signal to enable) /////////////////// // ide bus reset // /////////////////// configaddress = 0x40000044; // bit 31-11 : idsel specification = 010000000000000000000b // select pci device connected to ad30 // bit 10-08 : function number = 00b // bit 07-02 : register number = 17 (010001b), // -> ide reset register // (in the case of pci-ide asic board used in this application) // bit 01-00 : 00b (fixed)
chapter 5 application examples application note u17121ej1v1an 83 configdata = 0x00000001; // bit 0 : ide i/f reset port = 1b : // output ide resetx signal output to ide i/f. pci_configwrite(configaddress, configdata); return; } //////////////////////////////////// // transfer mode setting function // //////////////////////////////////// ///////////////////////////////////////////////////////////////////////// // function name: set_transfer_mode // // function: setting of transfer mode // // argument: dev_num : device selection (0:master/1:slave) // // mode : transfer mode // // return value: // // status_success : normal end // // status_timeout_device_selection : device selection error end // // status_timeout_drdy1 : drdy=1 timeout error end // // status_timeout_intrq : intrq timeout error end // // status_ide_error : error end after command execution // // // ///////////////////////////////////////////////////////////////////////// int set_transfer_mode(int dev_num, ubyte mode) { status = ata_set_features(dev_num, 0x03, mode); return status; } ///////////////////////////////////////////////////////////////// // function name: set_pio_timing // // function: setting of pio timing register // // argument: pio_timing : value set to pio timing register // // return value: none // // // ///////////////////////////////////////////////////////////////// void set_pio_timing(uword pio_timing) { uword configaddress; uword configdata; configaddress = 0x40000048; // bit 31-11 : idsel specification = 010000000000000000000b // select pci device connected to ad30 // bit 10-08 : function number = 00b
chapter 5 application examples application note u17121ej1v1an 84 // bit 07-02 : register number = 18 (010010b) // -> pio timing (in the case of pci-ide asic board used in this application) // bit 01-00 : 00b (fixed) pci_configwrite( configaddress, pio_timing ); return; } ///////////////////////////////////////////////////////////////////////// // function name: set_udma_timing // // function: setting of ultradma timing1, 2 registers // // argument: udma_timing1 : value set to ultradma timing1 register // // udma_timing2 : value set to ultradma timing2 register // // return value: none // // // ///////////////////////////////////////////////////////////////////////// void set_udma_timing(uword udma_timing1, uword udma_timing2) { uword configaddress; uword configdata; configaddress = 0x4000004c; // bit 31-11 : idsel specification = 010000000000000000000b // select pci device connected to ad30 // bit 10-08 : function number = 00b // bit 07-02 : register number = 19 (010011b) // -> ultradma timing1 // (in the case of pci-ide asic board used in this application) // bit 01-00 : 00b (fixed) pci_configwrite( configaddress, udma_timing11 ); configaddress = 0x40000050; // bit 31-11 : idsel specification = 010000000000000000000b // select pci device connected to ad30 // bit 10-08 : function number = 00b // bit 07-02 : register number = 20 (010100b) // -> ultradma timing2 // (in the case of pci-ide asic board used in this application) // bit 01-00 : 00b (fixed) pci_configwrite( configaddress, udma_timing2 ); return; } ////////////////////////////////////
chapter 5 application examples application note u17121ej1v1an 85 // ata command execution function // //////////////////////////////////// ///////////////////////////////////////////////////////////////////////// // function name: ata_set_features // // function: executes set features command (protocol:nd, command:efh). // // argument: dev_num : device selection (0:master/1:slave) // // return value: // // status_success : normal end // // status_timeout_device_selection : device selection error end // // status_timeout_drdy1 : drdy=1 timeout error end // // status_timeout_intrq : intrq timeout error end // // status_ide_error : error end after command execution // // // ///////////////////////////////////////////////////////////////////////// int ata_set_features(int dev_num, int sub_cmd, int mode) { int status; ata_command ac; ac.features = sub_cmd; // features register ac.sector_count = mode; // sectorcount register ac.sector_number = 0x00; // sectornumber register ac.cylinder_low = 0x00; // cylinderlow register ac.cylinder_high = 0x00; // cylinderhigh register ac.device_head = dev_num<<4; // device/head register ac.command = 0xef; // command register status = ata_pio_nondata(&ac); return status; } ////////////////////////////////////////////////////////////////////////// // function name: ata_idle_immediate // // function: executes idle immediate command (protocol:nd, command:e1h).// // argument: dev_num : device selection (0:master/1:slave) // // return value: // // status_success : normal end // // status_timeout_device_selection : device selection error end // // status_timeout_drdy1 : drdy=1 timeout error end // // status_timeout_intrq : intrq timeout error end // // status_ide_error : error end after command execution // // // ////////////////////////////////////////////////////////////////////////// int ata_idle_immediate(int dev_num) { ata_command ac;
chapter 5 application examples application note u17121ej1v1an 86 ac.features = 0x00; // features register ac.sector_count = 0x00; // sectorcount register ac.sector_number = 0x00; // sectornumber register ac.cylinder_low = 0x00; // cylinderlow register ac.cylinder_high = 0x00; // cylinderhigh register ac.device_head = dev_num<<4; // device/head register ac.command = 0xe1; // command register status = ata_pio_nondata(&ac); return status; } /////////////////////////////////////////////////////////////////////////// // function name: ata_identify_device // // function: executes identify device command (protocol:pi, command:ech).// // argument: dev_num : device selection (0:master/1:slave) // // buff : buffer pointer // // return value: // // status_success : normal end // // status_timeout_device_selection : device selection error end // // status_timeout_drdy1 : drdy=1 timeout error end // // status_timeout_intrq : intrq timeout error end // // status_ide_error : error end after command execution // // // /////////////////////////////////////////////////////////////////////////// int ata_identify_device(int dev_num, void *buff) { ata_command ac; int status; ac.features = 0x00; // features register ac.sector_count = 0x00; // sectorcount register ac.sector_number = 0x00; // sectornumber register ac.cyliner_low = 0x00; // cylinderlow register ac.cylinder_high = 0x00; // cylinderhigh register ac.dev_head = dev_num << 4; // device/head register ac.command = 0xec; // command register status = ata_pio_datain(&ac, 1, buff); return status; } ////////////////////////////////////////////////////////////////////////// // function name: ata_read_sector //
chapter 5 application examples application note u17121ej1v1an 87 // function: executes read sector(s) command (protocol:pi, command:20h).// // argument: dev_num : device selection (0:master/1:slave) // // lba : lba // // sec_cnt : number of sectors // // buff : buffer pointer // // return value: // // status_success : normal end // // status_timeout_device_selection : device selection error end // // status_timeout_drdy1 : drdy=1 timeout error end // // status_timeout_intrq : intrq timeout error end // // status_ide_error : error end after command execution // // // ////////////////////////////////////////////////////////////////////////// int ata_read_sector(int dev_num, uword lba, uhword sec_cnt, void *buff) { int status; ata_command ac; ac.features = 0x00; // features register ac.sector_count = sector_count; // sectorcount register ac.sector_number = (lba & 0xff); // sectornumber register ac.cylinder_low = (lba>>8 & 0xff); // cylinderlow register ac.cylinder_high = (lba>>16 & 0xff); // cylinderhigh register ac.device_head = 0x40|(dev_num<<4)|(lba>>24 & 0x0f); // device/head register ac.command = 0x20; // command register status = ata_pio_datain(&ac, sec_cnt, buff); return status; } /////////////////////////////////////////////////////////////////////////// // function name: ata_write_sector // // function: executes write sector(s) command (protocol:po, command:30h).// // argument: dev_num : device selection (0:master/1:slave) // // lba : lba // // sec_cnt : number of sectors // // buff : buffer pointer // // return value: // // status_success : normal end // // status_timeout_device_selection : device selection error end // // status_timeout_bsy0_drq0 : bsy=0,drq=0 timeout error end // // status_timeout_drdy1 : drdy=1 timeout error end // // status_timeout_intrq : intrq timeout error end // // status_ide_error : error end after command execution // // // /////////////////////////////////////////////////////////////////////////// int ata_write_sector(int dev_num, uword lba, uhword sec_cnt, void *buff) {
chapter 5 application examples application note u17121ej1v1an 88 int status; ata_command ac; ac.features = 0x00; // features register ac.sector_count = sector_count; // sectorcount register ac.sector_number = (lba & 0xff); // sectornumber register ac.cylinder_low = (lba>>8 & 0xff); // cylinderlow register ac.cylinder_high = (lba>>16 & 0xff); // cylinderhigh register ac.device_head = 0x40|(dev_num<<4)|(lba>>24 & 0x0f); // device/head register ac.command = 0x30; // command register status = ata_pio_dataout(&ac, sec_cnt, buff); return status; } ///////////////////////////////////////////////////////////////////////// // function name: ata_read_dma // // function: executes read dma command (protocol:dm, command:c8h). // // argument: dev_num : device selection (0:master/1:slave) // // lba : lba // // sec_cnt : number of sectors // // return value: // // status_success : normal end // // status_timeout_device_selection : device selection error end // // status_timeout_bsy0_drq0 : bsy=0,drq=0 timeout error end // // status_timeout_drdy1 : drdy=1 timeout error end // // status_timeout_intrq : intrq timeout error end // // status_timeout_bmend : bm timeout error end // // status_ide_error : error end after command execution // // // ///////////////////////////////////////////////////////////////////////// int ata_read_dma(int dev_num, uword lba, uhword sec_cnt) { int status; ata_command ac; ac.features = 0x00; // features register ac.sector_count = sector_count; // sectorcount register ac.sector_number = (lba & 0xff); // sectornumber register ac.cylinder_low = (lba>>8 & 0xff); // cylinderlow register ac.cylinder_high = (lba>>16 & 0xff); // cylinderhigh register ac.device_head = 0x40|(dev_num<<4)|(lba>>24 & 0x0f); // device/head register ac.command = 0xc8; // command register status = ata_dma(&ac); return status; }
chapter 5 application examples application note u17121ej1v1an 89 ///////////////////////////////////////////////////////////////////////// // function name: ata_write_dma // // function: executes write dma command (protocol:dm, command:cah). // // argument: dev_num : device selection (0:master/1:slave) // // lba : lba // // sec_cnt : number of sectors // // return value: // // status_success : normal end // // status_timeout_device_selection : device selection error end // // status_timeout_bsy0_drq0 : bsy=0,drq=0 timeout error end // // status_timeout_drdy1 : drdy=1 timeout error end // // status_timeout_intrq : intrq timeout error end // // status_timeout_bmend : bm timeout error end // // status_ide_error : error end after command execution // // // ///////////////////////////////////////////////////////////////////////// int ata_write_dma(int dev_num, uword lba, uhword sec_cnt) { int status; ata_command ac; ac.features = 0x00; // features register ac.sector_count = sector_count; // sectorcount register ac.sector_number = (lba & 0xff); // sectornumber register ac.cylinder_low = (lba>>8 & 0xff); // cylinderlow register ac.cylinder_high = (lba>>16 & 0xff); // cylinderhigh register ac.device_head = 0x40|(dev_num<<4)|(lba>>24 & 0x0f); // device/head register ac.command = 0xca; // command register status = ata_dma(&ac); return status; } ///////////////////////////////// // protocol execution function // ///////////////////////////////// ///////////////////////////////////////////////////////////////////////// // function name: ata_device_selection // // function: executes device selection protocol. // // argument: dev_num : (0:master / 1:slave) // // return value: // // status_success : normal end // // status_timeout_bsy0_drq0 : bsy=0,drq=0 timeout error end // // // ///////////////////////////////////////////////////////////////////////// int ata_device_selection(int dev_num) {
chapter 5 application examples application note u17121ej1v1an 90 int status; status = wait_ide_bsy0_drq0(); // wait until bsy=0, drq=0 if ( status != 0 ) { return status_timeout_bsy0_drq0; // timeout error end } *idereg_device_head = dev_num << 4; // device selection wait(timer400ns); // wait 400 ns status = wait_ide_bsy0_drq0(); // wait until bsy=0, drq=0 if ( status != 0 ) { return status_timeout_bsy0_drq0; // timeout error end } return status_success; // normal end } ///////////////////////////////////////////////////////////////////////// // function name: ata_pio_datain // // function: executes pio data in command protocol. // // argument: atacom : ata_command structure pointer // // sector_count : number of sectors // // buff : buffer pointer // // return value: // // status_success : normal end // // status_timeout_device_selection : device selection error end // // status_timeout_drdy1 : drdy=1 timeout error end // // status_timeout_intrq : intrq timeout error end // // status_ide_error : error end after command execution // // // ///////////////////////////////////////////////////////////////////////// int ata_pio_datain(ata_command *atacom, uhword sector_count, void *buff) { ubyte dev, idestat; uword *buffp; int i, j, status; buffp = (uword*)buff; dev = ( atacom->device_head >> 4 ) & 1; status = ata_device_selection(dev); // device selection if ( status != 0 ) { return status_timeout_device_selection; // device selection timeout } *idereg_features = atacom->features; // features register *idereg_sector_count = atacom->sector_count; // sectorcount register
chapter 5 application examples application note u17121ej1v1an 91 *idereg_sector_number = atacom->sector_number; // sectornumber register *idereg_cylinder_low = atacom->cylinder_low; // cylinderlow register *idereg_cylinder_high = atacom->cylinder_high; // cylinderhigh register status = wait_ide_drdy1(); // loop until drdy=1 if ( status != 0 ) { return status_timeout_drdy1 // drdy1 timeout } *idereg_command = atacom->command; // command register wait(timer400ns); // wait 400 ns for ( i=0; i chapter 5 application examples application note u17121ej1v1an 92 // // ///////////////////////////////////////////////////////////////////////// int ata_pio_dataout(ata_command *atacom, uhword sector_count, void *buff) { ubyte dev, idestat; uword *buffp; int i, j, status; buffp = (uword*)buff; dev = ( atacom->device_head >> 4 ) & 1; status = ata_device_selection(dev); // device selection if ( status != 0 ) { return status_timeout_device_selection; // device selection timeout } *idereg_features = atacom->features; // features register *idereg_sector_count = atacom->sector_count; // sectorcount register *idereg_sector_number = atacom->sector_number; // sectornumber register *idereg_cylinder_low = atacom->cylinder_low; // cylinderlow register *idereg_cylinder_high = atacom->cylinder_high; // cylinderhigh register status = wait_ide_drdy1(); // loop until drdy=1 if ( status != 0 ) { return status_timeout_drdy1; // drdy timeout } *idereg_command = atacom->command; // command register wait(timer400ns); // wait 400 ns status = wait_ide_bsy0_drq0(); // wait until bsy=0, drq=0 if ( status != 0 ) { return status_timeout_bsy0_drq0; // bsy timeout error end } for ( i=0; i chapter 5 application examples application note u17121ej1v1an 93 return status_ide_error(*idereg_error); // error end (after command execution) } return status_success; // normal end } ///////////////////////////////////////////////////////////////////////// // function name: ata_pio_nondata // // function: executes pio non data command protocol. // // argument: atacom : ata_command structure pointer // // return value: // // status_success : normal end // // status_timeout_device_selection : device selection error end // // status_timeout_drdy1 : drdy=1 timeout error end // // status_timeout_intrq : intrq timeout error end // // status_ide_error : error end after command execution // // // ///////////////////////////////////////////////////////////////////////// int ata_pio_nondata(ata_command *atacom) { int status; ubyte dev, idestat; dev = ( atacom->device_head >> 4 ) & 1; status = ata_device_selection(dev); // device selection if ( status != 0 ) { return status_timeout_device_selection; // device selection timeout } *idereg_features = atacom->features; // features register *idereg_sector_count = atacom->sector_count; // sectorcount register *idereg_sector_number = atacom->sector_number; // sectornumber register *idereg_cylinder_low = atacom->cylinder_low; // cylinderlow register *idereg_cylinder_high = atacom->cylinder_high; // cylinderhigh register status = wait_ide_drdy1(); // loop until drdy=1 if ( status != 0 ) { return status_timeout_drdy1; // drdy timeout } *idereg_command = atacom->command; // command register wait(timer400ns); // wait 400 ns status = wait_ide_intrq(); // wait for intrq assert if ( status != 0 ) { return status_timeout_intrq; // intrq timeout error }
chapter 5 application examples application note u17121ej1v1an 94 idestat = *idereg_alt_status; // alt status register empty read idestat = *idereg_status; // status register read if ( idestat & idereg_error_err_bit ) { return status_ide_error(*idereg_error); // error end (after command execution) } return status_success; // normal end } ///////////////////////////////////////////////////////////////////////// // function name: ata_dma // // function: executes dma command protocol. // // argument: atacom : ata_command structure pointer // // return value: // // status_success : normal end // // status_timeout_device_selection : device selection error end // // status_timeout_bsy0_drq0 : bsy=0,drq=0 timeout error end // // status_timeout_drdy1 : drdy=1 timeout error end // // status_timeout_intrq : intrq timeout error end // // status_timeout_bmend : bm timeout error end // // status_ide_error : error end after command execution // // // ///////////////////////////////////////////////////////////////////////// int ata_dma(ata_command *atacom) { int status; ubyte dev, idestat; dev = ( atacom->device_head >> 4 ) & 1; status = ata_device_selection(dev); // device selection if ( status != 0 ) { return status_timeout_device_selection; // device selection timeout } *idereg_features = atacom->features; // features register *idereg_sector_count = atacom->sector_count; // sectorcount register *idereg_sector_number = atacom->sector_number; // sectornumber register *idereg_cyl_low = atacom->cylinder_low; // cylinderlow register *idereg_cyl_high = atacom->cylinder_high; // cylinderhigh register status = wait_ide_drdy1(); // loop until drdy=1 if ( status != 0 ) { return status_timeout_drdy1; // drdy timeout } *idereg_command = atacom->command; // command register
chapter 5 application examples application note u17121ej1v1an 95 wait(timer400ns); // wait 400 ns idestat = *idereg_alt_status; // alt status register empty read *idereg_busmaster_start_stop |= 0x01; // bus master start status = wait_ide_bmend(); if ( status != 0 ) { return status_timeout_bmend; // bmend timeout error end } status = wait_ide_intrq(); // wait for intrq assert if ( status != 0 ) { return status_timeout_intrq; // intrq timeout error end } idestat = *idereg_alt_status; // alt status register empty read idestat = *idereg_status; // status register read if ( idestat & idereg_error_err_bit ) { return status_ide_error(*idereg_error); // error end (after command execution) } return status_success; // normal end } ///////////////////////////////////////////////////////////////// // function name: ata_soft_reset // // function: performs software reset. // // argument: none // // return value: // // status_success : normal end // // status_timeout_bsy0 : bsy=0 timeout error end // // // ///////////////////////////////////////////////////////////////// int ata_soft_reset(void) { int status; *idereg_device_control = 0x04; // reset execution wait(timer5ms); // wait 5 ms *idereg_device_control = 0x00; // reset release wait(timer5ms); // wait 5 ms status = wait_ide_bsy0(); // wait until bsy=0 if ( status != 0 ) { return status_timeout_bsy0; // timeout error end } return status_success; }
chapter 5 application examples application note u17121ej1v1an 96 ///////////////////////////////////////////////////////////////////////////////// // function name: main // // function: accesses ide hdd via pci bus and pci-ide asic board. // // argument: none // // return value: 0: normal end // // overview: issues idle immediate, identify device, set feature, read // // sector(s), write sector(s), read dma, and write dma commands. // // // ///////////////////////////////////////////////////////////////////////////////// int main(void) { int status; ubyte wbuff[4096], rbuff[4096]; discriptor_table* dsc_tbl; /////////////////////////// // system initialization // /////////////////////////// // initializes pci host bridge macro. pci_hbm_init(); // sets initialization of pci-ide asic board. pci_config_baseaddressinit(); pci_config_modeinit(); ata_soft_reset(void); // soft reset ////////////////////////////////// // issue ata command to ide hdd // ////////////////////////////////// //////////////////// // idle immediate // //////////////////// ata_idle_immediate(0); // issues idle immediate command. ///////////////////// // identify device // ///////////////////// ata_identify_device( // issues identify device command. 0, // master device buff // buffer storing results ); ////////////////////////////// // pio transfer preparation // //////////////////////////////
chapter 5 application examples application note u17121ej1v1an 97 // sets transfer mode to pio transfer mode0 using set_feature command. set_transfer_mode(0, pio_mode0); // sets pio timing register of configuration register of // pci-ide asic board. set_pio_timing(ide_pio_timing_ide33mhz_mode0); // buffer initialization initbuffer(wbuff, 4096); ////////////////// // pio transfer // ////////////////// ata_write_sector( // issues write sector command. 0, // master device 0, // lba 0 1, // 1 sector wbuff // buffer storing written contents ); ata_read_sector( // issues read sector command. 0, // master device 0, // lba 0 1, // 1 sector rbuff // buffer storing read results ); status = memcmp(wbuff, rbuff, 512); if ( status != 0 ) { printf("verify error!: write sector(s), read sector(s)\n"); } /////////////////////////////////// // ultradma transfer preparation // /////////////////////////////////// // sets transfer mode to ultradma transfer mode0 using set_feature command. set_transfer_mode(0, udma_mode0); // sets ultradma timing1 and ultradma timing2 registers of configuration // register of pci-ide asic board. set_udma_timing(ide_udma_timing1_ide33mhz_mode0, ide_udma_timing2_ide33mhz_mode0); //////////////////////////////// // pci->ide ultradma transfer // //////////////////////////////// // sets descriptor table referenced by pci-ide asic board during ultradma transfer. dsc_tbl = (discriptor_table*)(base_address_sdram + 0x02000000)
chapter 5 application examples application note u17121ej1v1an 98 dsc_tbl->transfer_address = base_address_sdram; dsc_tbl->transfer_byte = 0x1000; // = 4096byte = 8sector dsc_tbl->next_table_address = 0x00000001; // last table *idereg_dsctbl_start_address = dsc_tbl; // sets transfer direction of ultradma transfer. *idereg_busmaster_start_stop &= 0xfffffeff; // ultra dma (pci->ide) // buffer initialization initbuffer((ubyte*)dsc_tbl->transfer_address, 512*8); // issues command of ultradma transfer. ata_write_dma( 0, // master device 0, // lba 0 8, // 8 sector ); //////////////////////////////// // pci<-ide ultradma transfer // //////////////////////////////// // sets descriptor table referenced by device during ultradma transfer. dsc_tbl->transfer_address = base_address_sdram + 0x01000000; dsc_tbl->transfer_byte = 0x1000; // = 4096byte = 8sector dsc_tbl->next_table_address = 0x00000001; // last table *idereg_dsctbl_start_address = dsc_tbl; // sets transfer direction of ultradma transfer. *idereg_busmaster_start_stop |= 0x00000100; // ultra dma (pci<-ide) // issues command of ultradma transfer. ata_read_dma( 0, // master device 0, // lba 0 8, // 8 sector ); status = memcmp( (ubyte*)(base_address_sdram), (ubyte*)(base_address_sdram+0x01000000), 512*8); if ( status != 0 ) { printf("verify error!: write dma, read dma\n"); } return 0; }
chapter 5 application examples application note u17121ej1v1an 99 figure 5-6. ide_write_dma function 400 0000h 4096 bytes descriptor table 500 0000h 700 0000h 3ff ffffh 4ff ffffh 6ff ffffh 600 0000h 5ff ffffh 000 0000h ide hdd number of transfer bytes 0000 1000h write dma (data transfer from sdram to ide hdd) : transfer address 0400 0000h bus master transfer of 8 sectors (4096 bytes) is performed from 400 0000h (sdram area) to lba0 of ide hdd. figure 5-7. ide_read_dma function 400 0000h 4096 bytes descriptor table 500 0000h 600 0000h 3ff ffffh 4ff ffffh 5ff ffffh 700 0000h 6ff ffffh 000 0000h ide hdd read dma (data transfer from ide hdd to sdram) : bus master transfer of 8 sectors (4096 bytes) is performed from lba0 of ide hdd to 500 0000h (sdram area). number of transfer bytes 0000 1000h transfer address 0500 0000h

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